Apparatus and method of forming backside buried conductor in integrated circuit

1. An integrated circuit (IC) apparatus, comprising:

a substrate including a frontside and a backside;

at least one first insulating material deposited in the backside of the substrate in a form of a trench;

a conductive material deposited in each of the at least one first insulating material;

at least one second insulating material deposited on the conductive material to insulate the conductive material from the substrate;

an epitaxial crystalline material grown on the backside of the substrate;

at least one semiconductor component formed on the frontside; and

at least one via formed in the substrate to connect the conductive material to the at least one semiconductor component.

2. The IC apparatus of claim 1 , wherein the substrate is of a material selected from one of silicon (Si), germanium (Ge), and gallium arsenide (GaAs).

3. The IC apparatus of claim 1 , wherein the substrate has a thickness of less than or equal to 100 um.

4. The IC apparatus of claim 1 , wherein the at least one first insulating material and the at least one second insulating material are a dielectric material of silicon nitride (SiN).

5. The IC apparatus of claim 1 , wherein the conductive material is a refractory metal having a thermal stability greater than 900° C.

6. The IC apparatus of claim 1 , where the conductive material is tungsten (W) or ruthenium (Ru).

7. The IC apparatus of claim 1 wherein the conductive material is a power rail or a signal line.

8. The IC apparatus of claim 1 , wherein the at least one semiconductor component is a fin field effect transistor (FinFET) or a nanosheet FET.

9. The IC apparatus of claim 1 , wherein the at least one semiconductor component is formed using a single Damascene process or a dual Damascene process.

10. The IC apparatus of claim 1 , wherein the epitaxial crystalline material is grown to a thickness of less than or equal to 750 um.

11. A method of forming a conductive material in a backside of an integrated circuit (IC), comprising:

obtaining a substrate having a frontside and a backside;

etching at least one area of the substrate for at least one conductor;

depositing at least one first insulating material in the at least one etched area;

depositing conductive material in the at least one etched area;

depositing at least one second insulating material on the conductive material;

growing an epitaxial crystalline material on the backside of the substrate;

forming at least one semiconductor component in the frontside of the substrate that connects to the conductive material; and

forming at least one via in the substrate to connect the conductive material to the at least one semiconductor component.

12. The method of claim 11 , wherein the substrate is of a material selected from one of silicon (Si), germanium (Ge), and gallium arsenide (GaAs).

13. The method of claim 11 , wherein the substrate has a thickness of less than or equal to 100 um.

14. The method of claim 11 , wherein the at least one first insulating material and the at least one second insulating material are a dielectric material of silicon nitride (SiN).

15. The method of claim 11 , wherein the conductive material is a refractory metal having a thermal stability greater than 900° C.

16. The method of claim 11 , wherein the conductive material is tungsten (W) or ruthenium (Ru).

17. The method of claim 11 wherein the conductive material is a power rail or a signal line.

18. The method of claim 11 , wherein the at least one semiconductor component is a fin field effect transistor (FinFET) or a nanosheet FET.

19. The method of claim 11 , wherein the at least one semiconductor component is formed using a single Damascene process or a dual Damascene process.

20. The method of claim 11 , wherein the epitaxial crystalline material is grown to a thickness of less than or equal to 750 um.