Stacked FET with extremely small cell height
A microelectronic structure including a first stacked FET device that includes a first bottom FET device and a first upper FET device. The first bottom FET device include a plurality of first bottom channel layers, and the first upper FET device includes a plurality of first upper channel layers. A bottom gate that surrounds the plurality of first bottom channel layers and an upper gate that surrounds the plurality of first upper channel layers. A gate protrusion that extends downwards from the backside of the upper gate to connected to the bottom gate. The gate protrusion partially overlaps with a bottom gate cut region of the first bottom stacked FET device, and the gate protrusion partially overlaps with an upper gate cut region of the first upper stacked FET device.
1 . A microelectronic structure comprising:
a first stacked FET device that includes a first bottom FET device and a first upper FET device, wherein the first bottom FET device include a plurality of first bottom channel layers, wherein the first upper FET device includes a plurality of first upper channel layers;
a bottom gate that surrounds the plurality of first bottom channel layers;
an upper gate that surrounds the plurality of first upper channel layers; and
a gate protrusion that extends downwards from a backside of the upper gate to connected to the bottom gate, wherein the gate protrusion partially overlaps with a bottom gate cut region of the first bottom stacked FET device, and the gate protrusion partially overlaps with an upper gate cut region of the first upper stacked FET device.
2 . The microelectronic structure of claim 1 , further comprising:
a second stacked FET device that is located parallel to the first stacked FET device, wherein the second stacked FET device includes a second bottom FET device and second upper FET device, wherein the second bottom FET device include a plurality of second bottom channel layers, wherein the second upper FET device includes a plurality of second upper channel layers, wherein the second bottom FET device includes a fifth source/drain, wherein the second upper FET device includes a sixth source/drain;
a first source/drain contact connected to a backside surface of the first source/drain;
a second source/drain contact connected to the third source/drain, wherein the second source/drain contact is comprised of a first section and a second section, wherein the first section is connected a top surface and a sidewall of the third source/drain, wherein the second section is a via that extends to a backside of the first stacked FET device; and
a third source/drain contact that is connected to a top surface of the fifth source/drain.
3 . The microelectronic structure of claim 2 , further comprising:
a backside via contact located between the first source/drain and the fifth source/drain.
4 . The microelectronic structure of claim 2 , wherein a backside surface of the second section of the second source/drain contact is connected to a frontside surface of the backside via contact.
5 . The microelectronic structure of claim 1 , further comprising:
a bonding oxide layer that is located between the first bottom FET device and the first upper FET device.
6 . The microelectronic structure of claim 5 , wherein the protrusion of the upper gate is in contact with a frontside surface and a sidewall of the bottom gate.
7 . The microelectronic structure of claim 6 , wherein the first bottom channel layers have a first width across a gate region, wherein the first upper channel layers have a second width across the gate region.
8 . The microelectronic structure of claim 7 , wherein the first width is larger than the second width.
9 . A microelectronic structure comprising:
a first stacked FET device that includes a first bottom FET device and a first upper FET device, wherein the first bottom FET device include a plurality of first bottom channel layers, wherein the first upper FET device includes a plurality of first upper channel layers, wherein the first bottom FET device includes a first and second source/drain, wherein the first upper FET device includes a third and fourth source/drain, wherein the third and fourth source/drain have asymmetric shape, wherein the asymmetric shape of the third and fourth source/drain are comprised of a narrow section and a wide section, respectively;
a dielectric liner is located on sidewalls of the third and fourth source/drain, respectively; and
a first source/drain contact connected to the third source/drain, wherein the first source/drain contact is comprised of a first section and a second section, wherein the first section is connected to a top surface and a sidewall of the third source/drain, wherein the second section is a via that extends to a backside of the first stacked FET device.
10 . The microelectronic structure of claim 9 , further comprising:
a second stacked FET device that is located parallel to the first stacked FET device, wherein the second stacked FET device includes a second bottom FET device and second upper FET device, wherein the second bottom FET device include a plurality of second bottom channel layers, wherein the second upper FET device includes a plurality of second upper channel layers, wherein the second bottom FET device includes a fifth source/drain, wherein the second upper FET device includes a sixth source/drain;
a second source/drain contact connected to a backside surface of the first source/drain; and
a third source/drain contact that is connected to the fifth source/drain, wherein the third source/drain is comprised of a third section and a fourth section, wherein the third section is a via that extends from the second upper FET device towards the second bottom FET device, wherein the fourth section extends horizontally from the third section across a top surface of the fifth source/drain.
11 . The microelectronic structure of claim 9 , wherein the dielectric liner includes a first vertical segment located on a first side of the third source/drain, and the dielectric liner include a second vertical segment located on a second side of the third source/drain.
12 . The microelectronic structure of claim 11 , wherein a vertical height of the first vertical segment and a vertical height of the second vertical segment are different.
13 . The microelectronic structure of claim 12 , wherein the third source/drain is comprised of a first area and a second area, wherein the first area is sandwiched between the first vertical segment and the second vertical segment.
14 . The microelectronic structure of claim 13 , wherein the second area of third source/drain extends horizontal on top of the first vertical segment.
15 . The microelectronic structure of claim 14 , wherein the second first section of the first source/drain contact is in contact with the dielectric liner is in contact with the second vertical segment of the dielectric liner.
16 . The microelectronic structure of claim 15 , further comprising:
a bottom gate that surrounds the plurality of first bottom channel layers;
an upper gate that surrounds the plurality of first upper channel layers; and
a bonding oxide layer that is located between the first bottom FET device and the first upper FET device.
17 . The microelectronic structure of claim 16 , wherein the upper gate includes a protrusion that extends through the bonding oxide to connected to the bottom gate.
18 . The microelectronic structure of claim 17 , wherein the protrusion of the upper gate is in contact with a frontside surface and a sidewall of the bottom gate.
19 . A method comprising:
forming a first stacked FET device that includes a first bottom FET device and a first upper FET device, wherein the first bottom FET device include a plurality of first bottom channel layers, wherein the first upper FET device includes a plurality of first upper channel layers, wherein the first bottom FET device includes a first and second source/drain, wherein the first upper FET device includes a third and fourth source/drain;
forming a dielectric liner is located on sidewalls of the third and fourth source/drain, respectively, wherein the dielectric liner includes a first vertical segment located on a first side of the third source/drain, and the dielectric liner include a second vertical segment located on a second side of the third source/drain;
forming a second stacked FET device that is located parallel to the first stacked FET device, wherein the second stacked FET device includes a second bottom FET device and second upper FET device, wherein the second bottom FET device include a plurality of second bottom channel layers, wherein the second upper FET device includes a plurality of second upper channel layers, wherein the second bottom FET device includes a fifth source/drain, wherein the second upper FET device includes a sixth source/drain;
forming a first source/drain contact connected to a backside surface of the first source/drain;
forming a second source/drain contact connected to the third source/drain, wherein the second source/drain contact is comprised of a first section and a second section, wherein the first section is connected a top surface and a sidewall of the third source/drain, wherein the second section is a via that extends to a backside of first stacked FET device; and
forming a third source/drain contact that is connected to the fifth source/drain, wherein the third source/drain is comprised of a third section and a fourth section, wherein the third section is a via that extends from the second upper FET device towards the second bottom FET device, wherein the fourth section extends horizontally from the third section across a top surface of the fifth source/drain.
20 . The method of claim 19 , comprising:
pulling down the first vertical segment, such that, a vertical height of the first vertical segment and a vertical height of the second vertical segment are different.