Stacked-nanosheet semiconductor structures
Semiconductor structures and methods of making the same. The semiconductor structures including at least two vertically stacked nanosheet devices. In one embodiment, an integrated circuit includes a plurality of horizontal nanosheet devices (HNS devices) that are stacked vertically, on top of each other, relative to a top surface of a substrate. The plurality of HNS devices including a first HNS device and a second HNS device that each have source and drain structures.
1. A semiconductor structure that includes an erasable programmable read-only memory (EPROM) bit cell, the EPROM bit cell comprising:
a stacked pair of field-effect transistors including a first field-effect transistor (FET) and a second FET, the first FET having a first gate terminal connected to a word-line and a first source/drain terminal connected to a select-line;
wherein: the first and second FET are horizontal nano-sheet FETs (HNS-FETs).
2. The EPROM bit cell of claim 1 , wherein the first FET is an n-FET.
3. The EPROM bit cell of claim 2 , wherein the second FET is a p-FET.
4. The EPROM bit cell of claim 1 , wherein a second source/drain terminal of the first FET is connected to a first source/drain terminal of the second FET.
5. The EPROM bit cell of claim 4 , wherein a second source/drain terminal of the second FET is connected to a bit-line.
6. The EPROM bit cell of claim 1 , wherein a second gate terminal of the second FET is an electrically floating gate.
7. The EPROM bit cell of claim 6 , wherein the second gate terminal of the second FET is comprised of a storage dielectric.
8. The EPROM bit cell of claim 7 , wherein the storage dielectric includes quantum dots.
9. The EPROM bit cell of claim 7 , wherein the storage dielectric is comprised of silicon oxide having silicon nano-dots within the silicon oxide.
10. The EPROM bit cell of claim 9 , wherein the silicon oxide and the silicon nano-dots comprise an annealed flowable oxide.
11. A semiconductor structure including an erasable programmable read-only inverter, the erasable programmable read-only inverter comprising:
a stacked pair of field-effect transistors including a first field-effect transistor (FET) and a second FET, the first FET having a first gate terminal connected to an input line and a first source/drain terminal connected to a first power supply line;
wherein: the first and second FET are horizontal nano-sheet FETs (HNS-FETs).
12. The erasable programmable read-only inverter of claim 11 , wherein a second source/drain terminal of the first FET is connected to both of (i) a first source/drain terminal of the second FET and (ii) an output line.
13. The erasable programmable read-only inverter of claim 12 , wherein a second gate terminal of the second FET is an electrically floating gate, and a second source/drain terminal of the second FET is connected to a second power supply line.
14. The erasable programmable read-only inverter of claim 13 , wherein the second gate terminal of the second FET is comprised of a storage dielectric.
15. The erasable programmable read-only inverter of claim 14 , wherein the storage dielectric includes quantum dots.
16. The erasable programmable read-only inverter of claim 15 , wherein the storage dielectric is comprised of silicon oxide having silicon nano-dots within the silicon oxide.