Cryogenic detector with integrated backshort and method of manufacturing thereof

1. A method of manufacturing an integrated backshort, the method comprising:

providing a silicon wafer with a reflective metal layer bonded thereon, and with a silicon first layer deposited on said reflective metal layer;

depositing a structural second layer on said first layer;

depositing, patterning and etching a first superconductor layer on said second layer as a kinetic inductance detector (KID);

depositing and patterning a second superconductor layer on said second layer as one of leads, a microstrip, a capacitor or a filter; and

patterning and etching a phononic structure in said second layer and said first layer, leaving holes in said second layer;

wherein subsequent etching penetrates through said holes into said second layer, and into said first layer, and stopping on said reflective metal layer, leaving a space under said second layer where edges of said first layer which are etched under said second layer define a length of the integrated backshort.

2. The method of claim 1 , wherein prior to providing said silicon wafer, the method further comprises:

providing a silicon-on-insulator (SOI), including a first removable silicon wafer bonded to a silicon oxide layer, said silicon oxide layer which forms a bilayer with said silicon first layer;

depositing said metal reflective layer on said silicon-on-insulator to form a layered wafer;

turning over said layered wafer and removing said first removable silicon wafer and said silicon oxide layer, exposing said silicon first layer.

3. The method of claim 2 , the method further comprising:

bonding said first removable silicon wafer to said reflective metal layer using a polymer.

4. The method of claim 2 , the method further comprising:

removing said first removable silicon wafer and said silicon oxide layer using a hydrofluoric acid (HF) solution.

5. The method of claim 4 , the method further comprising:

coating and patterning a photoresist on said layered wafer; and

etching said second layer and said first layer by electron beam lithography and fluorine plasma and etching said photoresist layer with oxygen plasma.

6. The method of claim 5 , the method further comprising:

etching said first layer using a xenon fluoride (XeFe 2 ) gas phase chemistry;

wherein said holes allow for said xenon fluoride gas phase chemistry to react and etch said first layer isotropically, leaving a vacuum gap between said first superconductor layer and said reflective metal layer.

7. The method of claim 1 , wherein a thickness of said silicon wafer provides a quarter (¼) or three-quarter (¾) wave phase-delay of input light.

8. The method of claim 1 , wherein said structural material of said second layer comprises one of silicon nitride (SiN x ), an alloy including aluminum oxide (Al 2 O 3 ), a diamond or another dielectric material not including silicon.

9. The method of claim 8 , wherein said first superconductor layer is etched to function as a kinetic inductance detector (KID), and a thickness of said second layer is based on predetermined properties of a phononic crystal.

10. The method of claim 9 , wherein said second layer is deposited on said first layer using a low temperature process.

11. The method of claim 9 , wherein said reflective metal layer is a gold layer.

12. The method of claim 11 , wherein said first superconductor layer comprises hafnium (Hf).

13. The method of claim 12 , wherein said second superconductor layer comprises niobium (Nb).

14. An integrated backshort, the backshort comprising:

a silicon wafer;

a reflective metal layer bonded to said silicon wafer;

a silicon first layer disposed on said reflective metal layer;

a structural second layer disposed on said first layer;

a first superconductor layer disposed on said second layer as a kinetic inductance detector (KID); and

a second superconductor layer disposed on said second layer as one of leads, a microstrip, a capacitor or a filter;

wherein a phononic structure is etched in said second layer, leaving holes in said second layer; and

wherein subsequent etching penetrates through said holes into said second layer, and into said first layer, and stopping on said reflective metal layer, leaving a space under said second layer where edges of said first layer which are etched under said second layer define a length of the integrated backshort.

15. The integrated backshort of claim 14 , wherein said reflective metal layer comprises a gold layer.

16. The integrated backshort of claim 15 , wherein said first superconductor layer comprises hafnium (Hf).

17. The integrated backshort of claim 16 , wherein said second superconductor layer comprises niobium.

18. The integrated backshort of claim 17 , wherein said second layer comprises one of silicon nitride, an alloy including aluminum oxide (Al 2 O 3 ,) a diamond or another dielectric material not including silicon.

19. The integrated backshort of claim 18 , wherein said first superconductor layer is etched to function as a kinetic inductance detector (KID), and a thickness of said second layer is based on predetermined properties of a photonic crystal.

20. The integrated backshort of claim 15 , wherein a thickness of said silicon wafer provides a quarter (¼) or three-quarter (¾) wave phase-delay of input light.