Transistor display panel including lower electrode disposed under semiconductor and display device including the same
View Patent ↗A transistor display panel according to an exemplary embodiment includes: a substrate; a first transistor disposed on the substrate; and a pixel electrode connected to the first transistor, wherein the first transistor includes a lower electrode disposed on the substrate, a first semiconductor overlapping the lower electrode, a first insulating layer covering the first semiconductor, a first gate electrode disposed on the first insulating layer and overlapping the first semiconductor, and a first source connecting member and a first drain connecting member disposed on the same layer as the first gate electrode and connected to the first semiconductor, wherein the first gate electrode is formed as a triple layer, the first source connecting member and first drain connecting member are formed as a double layer, and the first source connecting member is connected to the lower electrode.
1. A transistor display panel comprising:
a substrate;
a lower electrode disposed on the substrate;
a buffer layer covering the lower electrode;
a transistor disposed on the substrate; and
a pixel electrode connected to the transistor,
wherein the transistor includes:
a semiconductor on the substrate,
a first insulating layer disposed on the semiconductor,
a gate electrode on the first insulating layer overlapping the semiconductor,
a connecting member disposed on the first insulating layer and connected to the semiconductor, the connecting member including a source connecting member and a drain connecting member,
a second insulating layer covering the gate electrode, the source connecting member and the drain connecting member, and
a source electrode and a drain electrode disposed on the second insulating layer,
wherein the lower electrode is disposed under the semiconductor and connected to the source connecting member,
wherein the semiconductor includes a channel, and a source region and a drain region disposed at respective sides of the channel,
wherein the source region and the drain region are respectively connected to the source connecting member and the drain connecting member,
wherein the source electrode is connected to the source connecting member, and
wherein the source connecting member is connected to the lower electrode through an opening of the buffer layer and the first insulating layer.
2. The transistor display panel of claim 1 , wherein
the gate electrode includes a main gate layer, and an upper gate layer and a lower gate layer respectively disposed on and under the main gate layer.
3. The transistor display panel of claim 2 , wherein
the source connecting member includes a main source connecting layer and a lower source connecting layer disposed thereunder, and
the drain connecting member includes a main drain connecting layer and a lower drain connecting layer disposed thereunder.
4. The transistor display panel of claim 3 , wherein
the main source connecting layer and the main drain connecting layer are disposed on the same layer as the main gate layer.
5. The transistor display panel of claim 1 , wherein the pixel electrode is connected to the source connecting member.
6. The transistor display panel of claim 5 , wherein the lower electrode is electrically connected to the pixel electrode.
7. The transistor display panel of claim 1 , further comprising:
a light-emitting diode element connected to the transistor and comprising the pixel electrode, an emission layer, and a common electrode.
8. The transistor display panel of claim 1 , further comprising:
a scan line disposed on the substrate;
a data line crossing the scan line; and
a second transistor connected to the scan line and the data line,
wherein the second transistor includes
a second semiconductor disposed on the same layer as the semiconductor,
a second gate electrode overlapping the second semiconductor, and
a second source connecting member and a second drain connecting member disposed on the same layer as the second gate electrode and connected to the second semiconductor.
9. The transistor display panel of claim 8 , wherein
the second gate electrode includes at least three layers, and the source connecting member and the drain connecting member include at least two layers.
10. The transistor display panel of claim 8 , wherein
the semiconductor and the second semiconductor include an oxide semiconductor material.
11. The transistor display panel of claim 1 , wherein
the lower electrode includes a metal having at least one among copper (Cu), copper alloys, aluminum (Al), aluminum alloys, molybdenum (Mo) and molybdenum alloys.
12. The transistor display panel of claim 11 , wherein
the gate electrode, the connecting member includes a metal layer having at least one of molybdenum (Mo) and titanium (Ti).
13. The transistor display panel of claim 12 , wherein
the pixel electrode includes a transparent conductive material having an indium tin oxide (ITO).
14. The transistor display panel of claim 1 , further comprising:
a storage capacitor connected to the gate electrode,
wherein one electrode of the storage capacitor is disposed on the same layer as the gate electrode.
15. The transistor display panel of claim 14 , wherein
the one electrode of the storage capacitor and the gate electrode are formed as one body.
16. The transistor display panel of claim 14 , wherein
the one electrode of the storage capacitor is extended from the gate electrode.
17. A display device comprising:
a substrate;
a lower electrode disposed on the substrate;
a buffer layer covering the lower electrode;
a semiconductor disposed on the buffer layer;
a first insulating layer disposed on the semiconductor;
a gate electrode disposed on the first insulating layer;
a second insulating layer covering the gate electrode;
a first electrode and a second electrode disposed on the second insulating layer and respectively connected to a first region and a second region of the semiconductor; and
a pixel electrode connected to the first electrode,
wherein the lower electrode is electrically connected to the first electrode and the pixel electrode, and
wherein the lower electrode is disposed on an opposite side of the gate electrode with respect to the semiconductor.
18. The display device of claim 17 , wherein
the first electrode is connected to the lower electrode through an opening of the buffer layer, the first insulating layer, and the second insulating layer.
19. The display device of claim 17 , further comprising:
an emission layer disposed on the pixel electrode, and
a common electrode disposed on the emission layer.
20. The display device of claim 17 , further comprising:
a scan line disposed on the substrate;
a data line crossing the scan line; and
a second transistor connected to the scan line and the data line,
wherein the second transistor includes
a second semiconductor disposed on the same layer as the semiconductor,
a second gate electrode overlapping the second semiconductor, and
a second source electrode and a second drain electrode disposed on the same layer as the first electrode and the second electrode.
21. The display device of claim 17 , wherein the lower electrode overlaps at least a part of a channel of the semiconductor in a plan view.