Structure and method for testing three-dimensional memory device
Embodiments of methods for testing three-dimensional memory devices are disclosed. The method can include: applying an input signal to a first conductive pad of the memory device by a first probe of a probe card; transmitting the input signal through the first conductive pad, a first TAC, a first interconnect structure passing through a bonding interface of the memory device, at least one of a memory array contact and a test circuit to a test structure; receiving an output signal through a second interconnect structure passing through the bonding interface, a second TAC, at least one of the memory array contact and the test circuit from the test structure; measuring the output signal from a second conductive pad of the memory device by a second probe of the probe card; and determining a characteristic of the test structure based on the input signal and the output signal.
1. A method for testing a memory device, comprising:
applying an input signal to a first conductive pad of the memory device by a first probe of a probe card;
transmitting, through at least the first conductive pad, a first through array contact (TAC) of the memory device, a first interconnect structure passing through a bonding interface between a memory array structure and a peripheral device structure of the memory device, and at least one of a memory array contact and a test circuit, the input signal to a test structure of the memory device;
receiving, through at least a second interconnect structure passing through the bonding interface, a second TAC of the memory device, and the at least one of the memory array contact and the test circuit, an output signal from the test structure;
measuring the output signal from a second conductive pad of the memory device by a second probe of the probe card; and
determining a characteristic of the test structure based on the input signal and the output signal.
2. The method of claim 1 , wherein at least part of the first conductive pad is on a top surface of the memory device.
3. The method of claim 1 , wherein at least part of the second conductive pad is on the top surface of the memory device.
4. The method of claim 1 , wherein the characteristic of the test structure comprises a resistance of an interconnect structure.
5. The method of claim 1 , wherein the characteristic of the test structure comprises a capacitance of an interconnect structure.
6. The method of claim 1 , wherein the characteristic of the test structure comprises a characteristic of a peripheral device electrically connected to the test circuit.
7. The method of claim 1 , wherein the characteristic of the test structure comprises a characteristic of a memory structure electrically connected to the memory array contact.
8. The method of claim 1 , wherein the memory array structure comprises:
a memory array stack;
the first TAC and the second TAC extending vertically through at least part of the memory array stack; and
the memory array contact.
9. The method of claim 8 , wherein the peripheral device structure comprises the test circuit.
10. The method of claim 9 , wherein the memory array structure is connected with the peripheral structure through an interconnect layer.
11. The method of claim 10 , wherein the interconnect layer includes the first interconnect structure, the second interconnect structure, and the bonding interface of the memory device.
12. The method of claim 11 , wherein each of the first interconnect structure and the second interconnect structure includes:
a first contact embedded in a first dielectric layer of the interconnect layer;
a second contact embedded in a second dielectric layer of the interconnect layer; and
a metal pattern embedded in a metal layer of the interconnect layer.
13. The method of claim 12 , wherein the bonding interface of the memory device is between the first dielectric layer and the second dielectric layer.
14. The method of claim 1 , wherein the memory array contact is a word line contact or a bit line contact.
15. The method of claim 1 , wherein the test circuit comprises at least one of a memory array structure test circuit and a contact signal path test circuit.
16. The memory device of claim 15 , wherein the memory array structure test circuit comprises at least one of a memory plane test circuit, a memory block test circuit, a bit line test circuit, and a word line test circuit.
17. The memory device of claim 12 , wherein the metal layer is disposed between the second dielectric layer and the memory array structure test circuit.