IP Library › Granted Patent US 10,999,939
Granted Patent B2
US 10,999,939 · App. 16/535,102 · Granted May 4, 2021

Circuit carrier board and manufacturing method thereof

Inventors: Chun-Hsien Chien (New Taipei, TW); Wen-Liang Yeh (Hsinchu, TW); Wei-Ti Lin (Hsinchu County, TW)
Assignee: Unimicron Technology Corp.
H05K3/4682H05K1/115H05K3/0047H05K3/4038H05K2201/09509
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Quick Facts
Patent No.
US 10,999,939
App. No.
16/535,102
Granted
May 4, 2021
Kind
B2
Abstract

A circuit carrier board includes a first build-up layer structure, a substrate, an adhesive layer, and a conductive structure. The first build-up layer includes a plurality of first dielectric layers and a plurality of first circuit layers original stacked. The substrate includes a base and a second build-up layer structure disposed on the base. The second build-up layer structure includes a plurality of second dielectric layers and a plurality of second circuit layer original stacked. A top most layer of the second circuit layers is exposed outside of the second dielectric layers. The conductive structure penetrates through the first dielectric layers, the first circuit layers and the adhesive layer, and contacts with the top most layer of the second circuit layers. The conductive structure electrical connects the first circuit layers to the second circuit layers. A manufacturing method of the circuit carrier board is also provided.

Claims (15)

1. A circuit carrier board comprising:

a first build-up layer structure comprising:

a plurality of first dielectric layers and a plurality of first circuit layers are alternately stacked, the first circuit layers are disposed in the first dielectric layers, and the first circuit layers are electrically connected to each other;

a substrate comprising:

a base;

a second build-up layer structure is disposed on the base, the second build-up layer structure comprising:

a plurality of second dielectric layers and a plurality of second circuit layers are alternately stacked, the second circuit layers are disposed in the second dielectric layers, and the second circuit layers are electrically connected to each other, wherein the topmost layer of the second circuit layers is exposed outside of the second dielectric layers;

an adhesive layer is disposed between the first build-up layer structure and the second build-up layer structure, the first build-up layer structure being bonded to the topmost layer of the second circuit layers;

a conductive structure penetrating the plurality of the first dielectric layers, the plurality of the first circuit layers, and the adhesive layer, and contacting the topmost layer of the second circuit layers,

wherein the conductive structure serially connects the first circuit layers in a direction perpendicular to the substrate,

wherein the conductive structure electrically connects the first circuit layers to the topmost layer of the second circuit layers.

2. The circuit carrier board according to claim 1 , further comprising a blind via, the vertical projection of the blind via on the base overlapping with the vertical projections of the first circuit layers and the topmost layer of the second circuit layers on the base, wherein the conductive structure is disposed in the blind via and electrically connected to the first circuit layers.

3. The circuit carrier board according to claim 1 , wherein the conductive structure has a top surface, a bottom surface opposite to the top surface, and a continuous sidewall connecting the top surface and the bottom surface, and the conductive structure is taper shaped.

4. The circuit carrier board according to claim 3 , wherein the top surface of the conductive structure has a first width, the bottom surface has a second width, and the first width is greater than the second width.

5. The circuit carrier board according to claim 1 , further comprising a solder resist layer partially covering the first build-up layer structure and the conductive structure, and the solder resist layer has a plurality of openings respectively partially exposing one of the first circuit layers and the conductive structure.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 8, 2019
From: CHIEN, CHUN-HSIEN; YEH, WEN-LIANG; LIN, WEI-TI
To: UNIMICRON TECHNOLOGY CORP.
Reel/Frame 049995/0845 →
Priority Claims (2)
TW 107136704 · Oct 18, 2018 · national
TW 108119700 · Jun 6, 2019 · national
Continuity (3)
Continuation In Part 16244113 · Jan 10, 2019
Provisional Application 62682181 · Jun 8, 2018
Related Publication 20190380212A1 · Dec 12, 2019