IP Library › Granted Patent US 11,004,736
Granted Patent B2
US 11,004,736 · App. 16/516,775 · Granted May 11, 2021

Integrated circuit having a single damascene wiring network

Inventors: Hsueh-Chung Chen (Cohoes, NY); Junli Wang (Slingerlands, NY); Somnath Ghosh (Clifton Park, NY); Chih-Chao Yang (Glenmont, NY); Lawrence A. Clevenger (Saratoga Springs, NY)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
H01L21/76879H01L21/76816H01L21/76831H01L21/76871H01L23/5226H01L23/5283H01L23/53209
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Quick Facts
Patent No.
US 11,004,736
App. No.
16/516,775
Granted
May 11, 2021
Kind
B2
Abstract

A method for fabricating a multi-layered wafer includes depositing a metal liner following by a seed layer including a metal in a trench arranged in an inter-metal dielectric (IMD). An end of the trench contacts a metal via of an interconnect structure. Heat is applied to drive the metal of the seed layer into the IMD and form a barrier layer along a sidewall of the trench.

Claims (18)

1. A method of fabricating a wafer, the method comprising:

depositing a metal liner followed by a seed layer in a trench arranged in an inter-metal dielectric (IMD), an end of the trench contacting a metal via of an interconnect structure, and the seed layer comprising a metal; and

applying heat to drive the metal of the seed layer into the IMD and form a barrier layer along sidewalls of the trench and at least partially along sidewalls of the metal via.

2. The method of claim 1 , wherein the seed layer comprises manganese, copper, or a combination thereof.

3. The method of claim 1 further comprising depositing another metal to fill the trench.

4. The method of claim 3 , wherein the another metal comprises copper, tungsten, aluminum, cobalt, ruthenium, rhodium, platinum, or any combination thereof.

5. The method of claim 1 , wherein the barrier layer comprises a compound that results from reaction of the metal in the seed layer and a compound of the IMD.

6. The method of claim 1 , wherein the seed layer is manganese.

7. The method of claim 1 , wherein the seed layer comprises copper and manganese.

8. A method of fabricating a wafer, the method comprising:

depositing a metal liner following by a seed layer in a trench arranged in an inter-metal dielectric (IMD), an end of the trench contacting a metal via of an interconnect structure, the metal via comprising a metal fill, the seed layer comprising a first metal and a second metal; and

applying heat to drive the first metal into the IMD and form a barrier layer along a sidewall of the trench and at least partially along sidewalls of the metal via, the second metal remaining in the seed layer.

9. The method of claim 8 , wherein the first metal of the seed layer comprises manganese.

10. The method of claim 9 , wherein the second metal of the seed layer comprises copper.

11. The method of claim 8 further comprising depositing another metal to fill the trench.

12. The method of claim 11 , wherein the another metal comprises copper, tungsten, aluminum, cobalt, ruthenium, rhodium, platinum, or any combination thereof.

13. The method of claim 8 , wherein the barrier layer comprises a compound that results from reaction of the first metal and a compound of the IMD.

14. The method of claim 8 , wherein the barrier layer comprises MnSiO 3 .

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 20, 2019
From: CHEN, HSUEH-CHUNG; WANG, JUNLI; GHOSH, SOMNATH; YANG, CHIH-CHAO; CLEVENGER, LAWRENCE A.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 049809/0839 →
Continuity (1)
Related Publication 20210020507A1 · Jan 21, 2021
Cited By (1)
US 12,598,984