Semiconductor package of package-on-package type

1. A semiconductor package comprising:

a first sub-package comprising:

a first package base substrate on which a first semiconductor chip is mounted, and

an electromagnetic wave shielding member having a top portion at a top surface of the first sub-package, side portions at side surfaces of the first sub-package, and bottom portions covering and directly contacting all of a bottom surface of the first sub-package, wherein a groove space extends inward from the bottom surface of the first sub-package; and

a second sub-package comprising a second package base substrate in the groove space and on which a second semiconductor chip is mounted,

wherein the second sub-package is connected to the first sub-package through an inter-package connection terminal attached to a first package connection pad on an innermost surface of the groove space of the first sub-package, and

wherein the second sub-package further comprises a molding member on the second package base substrate and surrounding the second semiconductor chip, the molding member being spaced apart from a lower surface and inner side surface of the groove space.

2. The semiconductor package of claim 1 , wherein the bottom surface of the first sub-package and a bottom surface of the second sub-package are at a same height.

3. The semiconductor package of claim 1 , further comprising an external connection terminal attached to a bottom surface of the second sub-package and protruding out from the groove space.

4. The semiconductor package of claim 1 , wherein:

the groove space extends from a bottom surface of the first package base substrate into the first package base substrate; and

a depth of the groove space is less than a thickness of the first package base substrate.

5. The semiconductor package of claim 1 , wherein the first sub-package further comprises:

an upper molding member on a top surface of the first package base substrate and surrounding the first semiconductor chip; and

a lower molding member on a bottom surface of the first package base substrate and defining the groove space.

6. The semiconductor package of claim 5 , wherein a portion of the bottom surface of the first package base substrate is exposed at the innermost surface of the groove space.

7. The semiconductor package of claim 1 , wherein the electromagnetic wave shielding member further has inner side portions extending from the bottom portions of the electromagnetic wave shielding member and covering portions of inner side surfaces of the groove space.

8. The semiconductor package of claim 1 , wherein side surfaces of the second sub-package are spaced apart from inner side surfaces of the groove space.

9. A semiconductor package comprising:

a first sub-package comprising:

a first package base substrate that is a unitary substrate,

a first semiconductor chip on the first package base substrate,

a first molding member on the first package base substrate and surrounding the first semiconductor chip, and

an electromagnetic wave shielding member covering a top surface of the first molding member, side surfaces of the first molding member, and side surfaces of the first package base substrate, wherein the first sub-package has a groove space extending inward from a bottom surface of the first package base substrate;

a second sub-package provided in the groove space and comprising:

a second package base substrate,

a second semiconductor chip on the second package base substrate, and

a second molding member on the second package base substrate and surrounding the second semiconductor chip, the second molding member being spaced apart from a lower surface and inner side surfaces of the groove space; and

an electromagnetic wave shielding terminal at the side surfaces of the first package base substrate and contacting the electromagnetic wave shielding member, the side surfaces of the first package base substrate being distinct from and perpendicular to the bottom surface of the first package base substrate, and a bottommost surface of the electromagnetic wave shielding terminal in contact with and within the first package base substrate,

wherein a bottom surface of the first sub-package and a bottom surface of the second sub-package are at a same height, and

wherein a topmost surface of the electromagnetic wave shielding terminal and a top surface of the first package base substrate are at a same height.

10. The semiconductor package of claim 9 , further comprising an external connection terminal attached to at least one of the bottom surface of the second sub-package and the bottom surface of the first package base substrate.

11. The semiconductor package of claim 9 , further comprising an external connection terminal attached to a bottom surface of the second package base substrate and protruding out from the groove space,

wherein the electromagnetic wave shielding member covers all of the bottom surface of the first package base substrate.

12. The semiconductor package of claim 9 , wherein the first sub-package and the second sub-package are electrically connected to each other by an inter-package connection terminal attached to an innermost surface of the groove space.

13. The semiconductor package of claim 12 , further comprising an under-fill layer disposed between the innermost surface of the groove space and the second sub-package and surrounding the inter-package connection terminal.

14. A semiconductor package comprising:

a first sub-package comprising:

a first package base substrate on which a first semiconductor chip is mounted, the first package base substrate being a unitary substrate,

an upper molding member on a top surface of the first package base substrate and surrounding the first semiconductor chip, and

an electromagnetic wave shielding member covering a top surface of the upper molding member, side surfaces of the upper molding member, and side surfaces of the first package base substrate;

a second sub-package comprising a second package base substrate on which a second semiconductor chip is mounted, and a molding member on the second package base substrate and surrounding the second semiconductor chip; and

an electromagnetic wave shielding terminal at the side surfaces of the first package base substrate and contacting the electromagnetic wave shielding member, the side surfaces of the first package base substrate being distinct from and perpendicular to a bottom surface of the first package base substrate, and a bottommost surface of the electromagnetic wave shielding terminal in contact with and within the first package base substrate,

wherein the first sub-package has a groove space extending inward from a bottom surface of the first sub-package,

wherein the molding member of the second sub-package is spaced apart from a lower surface and inner side surfaces of the groove space, and

wherein side surfaces of the second sub-package and the inner side surfaces of the groove space are spaced apart from each other in the groove space.

15. The semiconductor package of claim 14 , wherein:

the bottom surface of the first sub-package and a bottom surface of the second sub-package are at a same height; and

the electromagnetic wave shielding member covers all of the bottom surface of the first package base substrate.

16. The semiconductor package of claim 14 , wherein:

the first sub-package further comprises a lower molding member on the bottom surface of the first package base substrate and defining the groove space; and

the electromagnetic wave shielding member further covers side surfaces of the lower molding member and bottom surfaces of the lower molding member.