Integrated communication link testing
A test and measurement device includes an input configured to receive an analog signal from a Device Under Test (DUT), an Analog to Digital Converter (ADC) coupled to the input and structured to convert the analog signal to a digital signal, a receiver implemented in a first Field Programmable Gate Array (FPGA) and structured to accept the digital signal and perform signal analysis on the digital signal, a transmitter implemented in a second FPGA and structured to generate a digital output signal, and a Digital to Analog Converter (DAC) coupled to the transmitter and structured to convert the digital output signal from the transmitter to an analog signal, and structured to send the analog signal to the DUT. The receiver and the transmitter are coupled together by a high speed data link over which data about the current testing environment may be shared.
1. A test and measurement device, comprising:
an input configured to receive an analog signal from a Device Under Test (DUT);
an Analog to Digital Converter (ADC) coupled to the input and structured to convert the analog signal to a digital signal;
a receiver structured to accept the digital signal and perform signal conditioning, symbol recovery, and analysis on the digital signal using a first digital signal processor;
a transmitter structured to use a second digital signal processor to generate a digital output signal;
a Digital to Analog Converter (DAC) coupled to the transmitter and structured to convert the digital output signal from the transmitter to an analog signal, and structured to send the analog signal to the DUT; and
a communication path between the receiver and the transmitter that does not pass through the DUT;
in which at least portions of the first digital signal processor or second digital signal processor are physically embodied in a Field Programmable Gate Array.
2. The test and measurement device according to claim 1 , in which at least portions of the first digital signal processor are physically embodied in a reconfigurable processor.
3. The test and measurement device according to claim 1 , in which at least portions of the second digital signal processor are physically embodied in a reconfigurable processor.
4. The test and measurement device according to claim 1 , in which the transmitter and the receiver are housed in the same physical device.
5. The test and measurement device according to claim 1 , in which the transmitter and the receiver are housed in separate physical devices, and in which the communication path between the receiver and the transmitter is a wireless connection.
6. A test and measurement device, comprising:
an input configured to receive an analog signal from a Device Under Test (DUT);
an Analog to Digital Converter (ADC) coupled to the input and structured to convert the analog signal to a digital signal;
a receiver structured to accept the digital signal and, using a first digital signal processor, perform signal conditioning, symbol recovery, and analysis on the digital signal at a rate that is the same or exceeds a rate at which the analog signal is received from the DUT to continuously process the analog signal from the DUT.
7. The test and measurement device according to claim 6 , in which the receiver includes an eye diagram generator structured to continuously generate an eye diagram for the digital signal without halting receiving the analog signal from the DUT.
8. The test and measurement device according to claim 6 , in which the receiver includes a second input to receive a second analog signal from a second Device Under Test (DUT), in which the analog signal and the second analog signal respectively carry a first and a second portion of a signal according to a specific protocol, and in which the receiver is structured to recover protocol signals according to the specific protocol from the combination of the analog signal and the second analog signal.
9. A transmitter portion of a test and measurement device, comprising:
a signal generator structured to generate a base output signal;
a digital signal processor structured to add one or more impairments to the base output signal to form a combined output signal;
a Digital to Analog Converter (DAC) coupled to the digital signal processor and structured to convert the combined output signal to an analog signal, and to output the analog signal to a device for testing; and
an analog impairment emulator coupled to the DAC and structured to modify the analog signal prior to being output to the device for testing.
10. The transmitter portion of a test and measurement device according to claim 9 , further comprising a second signal generator to generate a second output signal, in which the base output signal and the second output signal each carry a portion of a protocol signal.
11. The transmitter portion of a test and measurement device according to claim 9 , in which the analog impairment emulator comprises a differential skew generator and in which a generated differential skew is added to the analog signal prior to being output to the device for testing.
12. The transmitter portion of a test and measurement device according to claim 9 , in which the analog impairment emulator comprises a common mode impairment emulator and in which a generated common mode impairment is added to the analog signal prior to being output to the device for testing.
13. The transmitter portion of a test and measurement device according to claim 9 , in which one of the one or more impairments comprises inter-symbol interference generated by an inter-symbol interference emulator.
14. The transmitter portion of a test and measurement device according to claim 9 , further comprising a clock generator, and in which the transmitter portion of the test and measurement device is structured to send a clock signal that is generated by the clock generator to the device for testing.
15. The transmitter portion of a test and measurement device according to claim 14 , further comprising a clock stress generator structured to modify the clock signal before being sent to the device for testing.
16. The transmitter portion of a test and measurement device according to claim 9 , further comprising a digital marker waveform generator, and in which the transmitter portion of the test and measurement device is structured to send a digital marker signal that is generated by the digital marker waveform generator to the device for testing.
17. The transmitter portion of a test and measurement device according to claim 16 , in which the digital marker signal is related to the analog signal.
18. The transmitter portion of a test and measurement device according to claim 17 , in which the digital marker signal is synchronized to the analog signal.
19. The transmitter portion of a test and measurement device according to claim 9 , further comprising a noise impairment waveform generator and in which a generated noise impairment is added to the analog signal prior to being output to the device for testing.