Analyzing bit error data to determine a root cause of errors in a digital system
Systems and methods are provided for detecting bit errors and further processing bit error information. A method, according to one implementation, includes the step of receiving a binary test sequence pattern generated by a pattern generator at an input to a digital communications system under test, wherein the binary test sequence pattern includes a plurality of sub-patterns. The method also includes the step of receiving an output binary sequence from an output of the digital communications system. Also, the method includes comparing the binary test sequence pattern with the output binary sequence to detect bit errors. Based on correlation characteristics between the bit errors and each of the sub-patterns, the method also includes the step of determining whether the bit errors are caused by random factors or are caused by deterministic factors associated with the digital communications system.
1 . A method comprising steps of:
receiving a binary test sequence pattern generated by a pattern generator at an input to a digital communications system under test, the binary test sequence pattern including a plurality of sub-patterns;
receiving an output binary sequence from an output of the digital communications system;
comparing the binary test sequence pattern with the output binary sequence to detect bit errors; and
based on correlation characteristics defined by a statistical relationship between the bit errors and occurrences of the plurality of sub-patterns, determining whether the bit errors are caused by random factors or are caused by deterministic factors associated with the digital communications system, wherein the correlation characteristics indicate random factors when the bit errors are substantially uniformly distributed across multiple sub-patterns, and indicate deterministic factors when the bit errors exhibit concentrated error peaks in one or more particular sub-patterns.
2 . The method of claim 1 , wherein each sub-pattern is configured to target certain types of deterministic factors associated with the digital communications system.
3 . The method of claim 2 , wherein the deterministic factors are related to a transmission bandwidth of the digital communications system.
4 . The method of claim 1 , wherein bit errors having error peaks focused on specific sub-patterns are indicative of errors caused by deterministic factors associated with the digital communications system.
5 . The method of claim 4 , further comprising the step of determining one or more remediation procedures with respect to the digital communications system for reducing a number of errors caused by the deterministic factors associated with the digital communications system.
6 . The method of claim 1 , further comprising the step of detecting one or more of a bit error rate and a bit error ratio, wherein the bit error rate is based on a number of detected bit errors per unit time and the bit error ratio is based on the number of detected bit errors versus a total number of bits in the binary test sequence pattern.
7 . The method of claim 1 , wherein the binary test sequence pattern is one of a Pseudo-Random Binary Sequence (PRBS) and a user-defined sequence, and wherein each of the sub-patterns has a predetermined binary sequence for targeting a specific characteristic of the digital communications system.
8 . The method of claim 1 , further comprising the step of analyzing the bit errors to extract metrics related to one or more of jitter, signal performance, and reflection.
9 . The method of claim 1 , further comprising the step of instructing the pattern generator to incorporate error correction code according to Forward Error Correction (FEC) techniques to reduce a number of bit errors.
10 . The method of claim 1 , wherein a first group of sub-patterns are defined as high-bandwidth sequences and a second group of sub-patterns are defined as low-bandwidth sequences.
11 . The method of claim 1 , wherein each sub-pattern is repeated in the binary test sequence pattern multiple times.
12 . The method of claim 1 , wherein bit errors that are caused by deterministic factors associated with the digital communications system are a result of one or more of transmission line faults, optical fiber faults, defective hardware, interference, distortion, reflection issues, bandwidth issues, and excessive attenuation, and wherein bit errors that are caused by random factors are a result of one or more of noise, jitter, environmental factors, and bit synchronization issues.
13 . The method of claim 1 , further comprising the step of synchronizing the binary test sequence pattern with the output binary sequence to enable the binary test sequence pattern to be compared with the output binary sequence.
14 . The method of claim 1 , wherein the binary test sequence pattern includes more than 10 20 bits.
15 . The method of claim 1 , wherein the binary test sequence pattern is applied to the input of the digital communications system at a rate of at least 10 Gbps.
16 . The method of claim 1 , further comprising the step of displaying waveforms indicative of the bit errors on an oscilloscope.
17 . An error testing device comprising:
a processing device; and
a memory device configured to store a computer program having instructions that, when executed, enable the processing device to
receive a binary test sequence pattern generated by a pattern generator at an input to a digital communications system under test, the binary test sequence pattern including a plurality of sub-patterns,
receive an output binary sequence from an output of the digital communications system,
compare the binary test sequence pattern with the output binary sequence to detect bit errors, and
based on correlation characteristics defined by a statistical relationship between the bit errors and occurrences of the plurality of sub-patterns, determine whether the bit errors are caused by random factors or are caused by deterministic factors associated with the digital communications system, wherein the correlation characteristics indicate random factors when the detected bit errors are distributed across multiple sub-patterns, and indicate deterministic factors when the detected bit errors are concentrated in one or more sub-patterns.
18 . The error testing device of claim 17 , wherein each sub-pattern is configured to target certain types of deterministic factors associated with the digital communications system, and wherein the deterministic factors are related to a transmission bandwidth of the digital communications system.
19 . A non-transitory computer-readable medium configured to store an error data analysis unit having computer logic that, when executed, enable one or more processing devices to:
receive a binary test sequence pattern generated by a pattern generator at an input to a digital communications system under test, the binary test sequence pattern including a plurality of sub-patterns;
receive an output binary sequence from an output of the digital communications system;
compare the binary test sequence pattern with the output binary sequence to detect bit errors; and
based on correlation characteristics representing a mapping between the bit errors and specific sub-patterns of the binary test sequence pattern, determine whether the bit errors are caused by random factors or are caused by deterministic factors associated with the digital communications system, wherein the correlation characteristics indicate deterministic factors when bit errors are concentrated within one or more sub-patterns, and indicate random factors when bit errors are relatively uniformly distributed across the plurality of sub-patterns.
20 . The non-transitory computer-readable medium of claim 19 , whereby bit errors having error peaks focused on sub-patterns are indicative of errors caused by deterministic factors associated with the digital communications system.