Apparatus and method for combining analog neural net with FPGA routing in a monolithic integrated circuit
A user programmable integrated circuit includes a user-programmable routing network including a plurality of interconnect conductors selectively couplable to one another by user-programmable elements. A plurality of matrix vector multipliers, each have a plurality of word lines, each word line coupled to a different first one of the one of the interconnect conductors of the user-programmable routing network, the word lines forming intersections with a plurality of summing bit lines, a programmable Vt transistor at each intersection having a gate connected to the intersecting word line, a source connected to a fixed potential and a drain connected to the intersecting summing bit line. A charge-to-pulse-width converter circuit is associated with each one of the matrix vector multipliers, each having an input coupled to one of the summing bit lines, and a pulse output coupled to a different second one of the interconnect conductors of the user-programmable routing network.
1. A user programmable integrated circuit comprising:
a user-programmable routing network including a plurality of interconnect conductors selectively couplable to one another by user-programmable elements;
a plurality of matrix vector multipliers, each matrix vector multiplier including a plurality of word lines, each word line coupled to a different first one of the interconnect conductors of the user-programmable routing network, the word lines forming intersections with a plurality of summing bit lines, a programmable Vt transistor at each intersection having a gate connected to the intersecting word line, a source connected to a fixed potential and a drain connected to the intersecting summing bit line; and
a plurality of charge-to-pulse-width converter circuits, each being associated with one of the matrix vector multipliers, each having an input coupled to one of the summing bit lines, and a pulse output coupled to a different second one of the interconnect conductors of the user-programmable routing network.
2. The user-programmable integrated circuit of claim 1 wherein the inputs of the charge-to-pulse-width converter circuits associated with each one of the matrix vector multipliers are each coupled to one of the summing bit lines through an inverter.
3. The user-programmable integrated circuit of claim 1 wherein the plurality of word lines in each matrix vector multiplier are coupled to the different first one of the interconnect conductors of the user-programmable routing network through inverters.
4. The user-programmable integrated circuit of claim 1 wherein a first matrix vector multiplier of the plurality of matrix vector multipliers comprises a plurality of word lines, the word lines forming intersections with a plurality of summing bit lines, a programmable Vt transistor at each intersection having a gate connected to the intersecting word line, a source connected to a fixed potential and a drain connected to the intersecting summing bit line, and
a plurality of pulse generator circuits each have an output coupled to each of the word lines of the first matrix vector multiplier, each configured to generate a digital pulse having a pulse width proportional to an analog quantity to be input to a neural network including at least the first matrix vector multiplier.
5. The user-programmable integrated circuit of claim 4 wherein each pulse generator circuit comprises a digital pulse generator circuit.
6. The user-programmable integrated circuit of claim 5 wherein each pulse generator circuit comprises:
an n-bit storage element storing an n-bit count value representing a pulse width;
an n-bit counter having n outputs;
an n-bit digital comparator having a first set of n data inputs, a second set of n data inputs and an output, the first set of n data inputs coupled to the n outputs of the n-bit storage element, the second set of n data inputs coupled to the n outputs of the n-bit counter, the output serving as the output of the pulse generator circuit.
7. The user-programmable integrated circuit of claim 4 wherein each pulse generator circuit comprises an analog pulse generator circuit.
8. The user-programmable integrated circuit of claim 7 wherein each pulse generator circuit comprises:
a voltage follower operational amplifier having an input coupled to an analog input voltage;
a first switch configured to charge a capacitor during a charge collection time frame;
a second switch configured to discharge the capacitor at a constant current during an analog pulse generating time frame;
a comparator coupled to the capacitor to indicate when the capacitor has been discharged; and
a logic gate configured to output the analog pulse during the analog pulse generating time frame until the comparator indicates that the capacitor has been discharged.
9. A user programmable integrated circuit comprising:
a user-programmable routing network including a plurality of interconnect conductors selectively couplable to one another by user-programmable elements;
a plurality of matrix vector multipliers, each matrix vector multiplier including a plurality of word lines, each word line coupled to a different first one of the interconnect conductors of the user-programmable routing network, the word lines forming intersections with a plurality of summing bit lines, a programmable Vt transistor at each intersection having a gate connected to the intersecting word line, a source connected to a fixed potential and a drain connected to the intersecting summing bit line; and
a plurality of charge-to-pulse-width converter circuits, each being associated with one of the matrix vector multipliers, each having an input coupled to one of the summing bit lines, and a pulse output coupled to a different second one of the interconnect conductors of the user-programmable routing network,
each charge-to-pulse-width converter circuit including:
a slave current mirror section mirroring current from a master current mirror section;
a first switch coupling a capacitor to the input of the charge-to-pulse-width converter circuit to charge the capacitor during a charge collection time frame;
a second switch coupling the capacitor to the slave current mirror section to discharge the capacitor at a constant current during an analog pulse generating time frame;
a comparator coupled to the capacitor to indicate when the capacitor has been discharged; and
a logic gate configured to output the analog pulse during the analog pulse generating time frame until the comparator indicates that the capacitor has been discharged.
10. The user-programmable integrated circuit of claim 9 , further comprising a switch in each charge-to-pulse-width converter circuit to shift voltage stored on the capacitor sensed by the comparator during the analog pulse generating time frame.
11. The user-programmable integrated circuit of claim 9 wherein the inputs of the charge-to-pulse-width converter circuits associated with each one of the matrix vector multipliers are each coupled to one of the summing bit lines through an inverter.
12. The user-programmable integrated circuit of claim 9 wherein the plurality of word lines in each matrix vector multiplier are coupled to a different first one of the interconnect conductors of the user-programmable routing network through inverters.