Granted Patent B2

US 12,237,011 · App. 17/853,315 · Granted Feb 25, 2025

Inventors: Hieu Van Tran (San Jose, CA); Thuan Vu (San Jose, CA); Stanley Hong (San Jose, CA); Stephen Trinh (San Jose, CA); Anh Ly (San Jose, CA); Han Tran (Ho Chi Minh, VN); Kha Nguyen (Ho Chi Minh, VN); Hien Pham (Ho Chi Minh, VN)

Assignee: SILICON STORAGE TECHNOLOGY, INC.

G11C11/5642G06F17/16G06N3/06G11C11/1655G11C11/1657G11C11/4074

Abstract

Claims (16)

1. A system comprising:

a plurality of vector-by-matrix multiplication arrays in an analog neural memory system, respective ones of the plurality of vector-by-matrix multiplication comprising an array of non-volatile memory cells organized into rows and columns, wherein the plurality of vector-by-matrix multiplication arrays share control gate lines and source lines;

a shared high voltage row decoder coupled to the control gate lines and the source lines of the plurality of vector-by-matrix multiplication arrays to apply a first set of voltages to control gate terminals, source line terminals, and erase gate terminals of one or more selected rows in the plurality of vector-by-matrix multiplication arrays during a program operation;

a plurality of read row decoders, each read row decoder coupled to read word lines and word line terminals of one of the arrays in the plurality of vector-by-matrix multiplication arrays but not the other arrays in the plurality of vector-by-matrix multiplication arrays to apply a second voltage lower than each of the first set of voltages to word line terminals of one or more selected rows in the one of the arrays during a read operation; and

a shared program row decoder coupled to all of the arrays in the plurality of vector-by-matrix multiplication arrays to apply a third voltage lower than each of the first set of voltages to word line terminals of one or more selected rows in one or more of the vector-by-matrix multiplication arrays during a program operation;

wherein the read word lines are perpendicular to the control gate lines and the source lines.

2. The system of claim 1 , wherein the non-volatile memory cells are split-gate flash memory cells.

3. The system of claim 1 , wherein the non-volatile memory cells are stacked-gate flash memory cells.

4. A method comprising:

applying, by a shared program row decoder coupled to a plurality of vector-by-matrix multiplication arrays of non-volatile memory cells that share control gate lines, erase gate lines, and source lines, a first voltage during a program operation to word lines coupled to one or more selected rows in one or more of the plurality of vector-by-matrix multiplication arrays;

applying, by a shared high voltage row decoder to the control gate lines, erase gate lines, and source lines of the plurality of vector-by-matrix multiplication arrays of non-volatile memory cells, a set of voltages during a program operation to one or more selected rows in one or more of the plurality of vector-by-matrix multiplication arrays; and

applying, by a read row decoder, a second voltage received from read word lines to word lines coupled to one or more selected rows of non-volatile memory cells in one of the arrays in the plurality of vector-by-matrix multiplication arrays but not the other arrays in the plurality of vector-by-matrix multiplication arrays during a read operation;

wherein the read word lines are perpendicular to the control gate lines and the source lines; and

wherein each voltage in the set of voltages is larger than the first voltage and the second voltage.

5. The method of claim 4 , wherein the non-volatile memory cells are split-gate flash memory cells.

6. The method of claim 4 , wherein the non-volatile memory cells are stacked-gate flash memory cells.

Assignments (1)

Continuity (3)

References Cited (155)