3D semiconductor device and structure
A 3D semiconductor device, the device including: a first level including a single crystal layer, a first metal layer, a second metal layer above the first metal layer, and a third metal layer above the second metal layer, where the second metal layer is significantly thicker than either the third metal layer or the first metal layer, where the third metal layer is precisely aligned to the first metal layer with less than 20 nm misalignment; a second level including a first array of first memory cells, each of the first memory cells include first transistors; a third level including a second array of second memory cells, each of the second memory cells include second transistors, where the second level is above the third level, where the second transistors are self-aligned to the first transistors, being processed following the same lithography step; and periphery circuits connected by the second metal to control the memory cells, where the periphery circuits are either underneath or atop the memory cells.
1. A 3D semiconductor device, the device comprising;
a first level comprising a single crystal layer, a first metal layer, a second metal layer above said first metal layer, and a third metal layer above said second metal layer,
wherein said second metal layer is significantly thicker than either said third metal layer or said first metal layer;
a second level comprising a first array of first memory cells, each of said first memory cells comprise first transistors; and
a third level comprising a second array of second memory cells, each of said second memory cells comprise second transistors,
wherein said second level is above said third level,
wherein said second transistors are self-aligned to said first transistors, being processed following a same lithography step,
wherein said first level comprises third transistors,
wherein said first metal layer provides connections to said third transistors for a construction of periphery circuits,
wherein connections from said periphery circuits to said first memory cells and said second memory cells comprise said second metal, said periphery circuits and said second metal are adapted to control said first memory cells and said second memory cells, and
wherein said periphery circuits are directly underneath said first memory cells and said second memory cells.
2. The 3D semiconductor device according to claim 1 ,
wherein at least one of said second transistors comprises a source, a channel, and a drain, and
wherein said source, said channel, and said drain have a same dopant type.
3. The 3D semiconductor device according to claim 1 ,
wherein said first level comprises through silicon vias (TSVs) providing connections to an external device.
4. The 3D semiconductor device according to claim 1 ,
wherein said significantly thicker is at least 100% thicker.
5. The 3D semiconductor device according to claim 1 ,
wherein at least one of said first transistors comprises a source, a channel, and a drain, and
wherein said source, said channel, and said drain have a same dopant type.
6. The 3D semiconductor device according to claim 1 , further comprising:
a fourth level disposed above said second level,
wherein said fourth level comprises a single crystal silicon layer.
7. The 3D semiconductor device according to claim 1 , further comprising:
a fourth level disposed above said third level,
wherein said fourth level comprises a single crystal silicon layer, and
wherein said fourth level comprises through silicon vias (TSVs) providing connections to an external device.
8. A 3D semiconductor device, the device comprising;
a first level comprising a single crystal layer, a first metal layer, a second metal layer above said first metal layer, and a third metal layer above said second metal layer,
wherein said second metal layer has a significantly greater current carrying capacity than either said third metal layer or said first metal layer;
a second level comprising a first array of first memory cells, each of said first memory cells comprise first transistors;
a third level comprising a second array of second memory cells, each of said second memory cells comprise second transistors,
wherein said second level is above said third level,
wherein said second transistors are self-aligned to said first transistors, being processed following a same lithography step; and
a fourth level comprising periphery circuits, said periphery circuits comprise connections by said second metal,
wherein said periphery circuits are adapted to control said first memory cells and said second memory cells, and
wherein said periphery circuits are atop said first memory cells and said second memory cells.
9. The 3D semiconductor device according to claim 8 ,
wherein at least one of said second transistors comprises a source, a channel, and a drain, and
wherein said source, said channel, and said drain have a same dopant type.
10. The 3D semiconductor device according to claim 8 ,
wherein at least one of said second transistors comprises a polysilicon channel.
11. The 3D semiconductor device according to claim 8 ,
wherein said significantly greater current comprises at least 50% higher current carrying capacity of interconnect wire made by said second metal layer compared to current carrying capacity of interconnect wire made by said first metal layer or said third metal layer.
12. The 3D semiconductor device according to claim 8 ,
wherein at least one of said first transistors comprises a source, a channel, and a drain, and
wherein said source, said channel, and said drain have a same dopant type.
13. The 3D semiconductor device according to claim 8 ,
wherein said first level is below said third level.
14. The 3D semiconductor device according to claim 8 , further comprising:
connections to an external device,
wherein said connections are above said fourth level and provide connections from said external device to said periphery circuits.
15. A 3D semiconductor device, the device comprising;
a first level comprising a single crystal layer, a first metal layer, a second metal layer above said first metal layer, and a third metal layer above said second metal layer,
wherein said second metal layer is significantly thicker than either said third metal layer or said first metal layer;
a second level comprising a first array of first memory cells, each of said first memory cells comprise first transistors;
a third level comprising a second array of second memory cells, each of said second memory cells comprise second transistors,
wherein said second level is above said third level,
wherein said second transistors are self-aligned to said first transistors, being processed following a same lithography step; and
periphery circuits connected by said second metal to control said first memory cells and said second memory cells,
wherein said periphery circuits are either underneath said first memory cells and said second memory cells or atop said first memory cells and said second memory cells.
16. The 3D semiconductor device according to claim 15 ,
wherein at least one of said second transistors comprises a source, a channel, and a drain, and
wherein said source, said channel, and said drain have a same dopant type.
17. The 3D semiconductor device according to claim 15 ,
wherein at least one of said second transistors comprises a polysilicon channel.
18. The 3D semiconductor device according to claim 15 ,
wherein said significantly thicker is at least 50% thicker.
19. The 3D semiconductor device according to claim 15 ,
wherein said periphery circuits are underneath said first memory cells and said second memory cells.
20. The 3D semiconductor device according to claim 15 ,
wherein said first memory cells and said second memory cells are non-volatile NAND memory type cells.