Package substrate having copper alloy sputter seed layer and high density interconnects
Integrated circuit (IC) package substrates having high density interconnects with a sputter seed layer containing a copper alloy, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, a package substrate may include a first dielectric layer, a sputter seed layer disposed on the first dielectric layer, wherein the seed layer includes a copper alloy, a patterned conductive layer disposed on the seed layer, and a second dielectric layer over the patterned conductive layer.
1. An integrated circuit (IC) package substrate, comprising:
a first dielectric layer;
a seed layer formed on the first dielectric layer, wherein the seed layer comprises a copper alloy, and wherein a top surface of the seed layer is roughened;
a patterned conductive layer formed on the seed layer; and
a second dielectric layer formed on the first dielectric layer and the patterned conductive layer.
2. The IC package substrate of claim 1 , wherein the copper alloy comprises one or more of manganese, cobalt, ruthenium, tungsten, or aluminum.
3. The IC package substrate of claim 1 , wherein a thickness of the seed layer is less than 0.5 um.
4. The IC package substrate of claim 1 , wherein the top surface of the seed layer is roughened during formation.
5. The IC package substrate of claim 1 , wherein the top surface of the seed layer is roughened after formation by low ion bombardment.
6. The IC package substrate of claim 1 , wherein the patterned conductive layer includes a first conductive trace, a second conductive trace, and a space between the first and the second conductive traces, and wherein a line space width of the first conductive trace and the space between the first and the second conductive traces is 2/2 um.
7. The IC package substrate of claim 1 , wherein the patterned conductive layer includes a conductive trace, and wherein a thickness of the second dielectric layer is approximately equal to a width of the conductive trace.
8. An integrated circuit (IC) device, comprising:
a package substrate, the package substrate comprising:
a first dielectric layer;
a seed layer formed on the first dielectric layer, wherein the seed layer comprises a copper alloy, and wherein a top surface of the seed layer is roughened;
a patterned conductive layer formed on the seed layer; and
a second dielectric layer formed on the first dielectric layer and the patterned conductive layer; and
a die coupled to the package substrate.
9. The IC device of claim 8 , wherein the copper alloy comprises one or more of manganese, cobalt, ruthenium, tungsten, or aluminum.
10. The IC device of claim 8 , wherein a thickness of the seed layer is less than 0.5 um.
11. The IC device of claim 8 , wherein the seed layer is a first seed layer, the IC device further comprising:
a second seed layer formed on the second dielectric layer, wherein the second seed layer comprises a copper alloy.
12. The IC device of claim 8 , wherein the seed layer comprises more than one layer.
13. The IC device of claim 12 , wherein a first layer of the seed layer comprises copper and a second layer of the seed layer comprises copper alloy.
14. The IC device of claim 12 , wherein a first layer of the seed layer comprises a first copper alloy and a second layer of the seed layer comprises a second copper alloy.
15. The IC device of claim 14 , wherein the first copper alloy and the second copper alloy are different alloys.
16. A method of forming an integrated circuit package substrate, the method comprising:
forming a first dielectric layer;
sputtering a seed layer over the first dielectric layer, wherein the seed layer comprises a copper alloy;
depositing and patterning a first photoresist layer to expose a portion of the seed layer;
depositing a first conductive material into the exposed portion of the first photoresist layer to form a patterned conductive layer over the seed layer;
removing the first photoresist layer;
depositing and patterning a second photoresist layer to expose at least a portion of the patterned conductive layer;
depositing a second conductive material into the exposed portion of the second photoresist layer to form a conductive via;
removing the second photoresist layer;
etching portions of the seed layer;
forming a second dielectric layer over the patterned conductive layer and the conductive via; and
recessing the second dielectric layer to expose a top surface of the conductive via.
17. The method of claim 16 , wherein the seed layer is a first seed layer, the method further comprising sputtering a second seed layer over the second dielectric layer and the top surface of the conductive via, wherein the second seed layer comprises a copper alloy.
18. The method of claim 17 , further comprising:
depositing a third photoresist layer and patterning the third photoresist layer to expose at least a portion of the second seed layer;
depositing a third conductive material into the exposed portion of the third photoresist layer to form a patterned second conductive layer over the second seed layer;
removing the third photoresist layer;
depositing a fourth photoresist layer and patterning the fourth photoresist layer to expose at least a portion of the patterned second conductive layer;
depositing a fourth conductive material into the exposed portion of the fourth photoresist layer to form a second conductive via;
removing the fourth photoresist layer;
etching portions of the second seed layer;
forming a third dielectric layer over the patterned second conductive layer and the second conductive via; and
recessing the second dielectric layer to expose a top surface of the second conductive via.
19. The method of claim 16 , wherein the copper alloy comprises one or more of manganese, cobalt, ruthenium, tungsten, or aluminum.
20. The method of claim 16 , wherein a thickness of the seed layer is less than 0.5 um.