Resistive random access memory device

1. A memory cell, comprising:

a resistive material layer comprising a first portion that extends along a first direction and a second portion that extends along a second direction;

a first electrode coupled to a bottom surface of the first portion of the resistive material layer;

a second electrode coupled to the second portion of the resistive material layer;

a first capping layer comprising at least a portion that is coupled between the first electrode and the first portion of the resistive material layer; and

a second capping layer comprising at least a portion that is coupled between the second portion of the resistive material layer and the second electrode.

2. The memory cell of claim 1 , wherein the first and second directions are substantially perpendicular to each other.

3. The memory cell of claim 1 , wherein the resistive material layer presents a variable resistance value.

4. The memory cell of claim 1 , wherein the first and second electrodes are in parallel to each other.

5. The memory cell of claim 1 , further comprising:

a transistor, wherein the second electrode is coupled to a drain feature or a source feature of the transistor.

6. The memory cell of claim 1 , wherein the portion of the first capping layer extends along the first direction, and the portion of the second capping layer extends along the second direction.

7. The memory cell of claim 1 , wherein the resistive material layer comprises at least one material selected from the group consisting of: ZrO 2 , NiO, TiO 2 , HfO, ZrO, ZnO, WO 3 , CoO, Nb 2 O 5 , Fe 2 O 3 , CuO, CrO 2 , or SrZrO 3 .

8. A memory device, comprising:

a first resistive material layer and a second resistive material layer that are laterally spaced from each other by a dielectric structure,

wherein the first and second resistive material layers each comprises a horizontal portion and a vertical portion;

a first electrode coupled to a bottom surface of the horizontal portions of the first and second resistive material layers;

a second electrode coupled to the vertical portion of the first resistive material layer, wherein the first resistive material layer, the first electrode, and the second electrode form a first resistive random access memory (RRAM) resistor; and

a third electrode coupled to the vertical portion of the second resistive material layer, wherein the second resistive material layer, the first electrode, and the third electrode form a second RRAM resistor.

9. The memory cell of claim 8 , wherein each of the first and second resistive material layers comprises at least one material selected from the group consisting of: ZrO 2 , NiO, TiO 2 , HfO, ZrO, ZnO, WO 3 , CoO, Nb 2 O 5 , Fe 2 O 3 , CuO, CrO 2 , or SrZrO 3 .

10. The memory device of claim 8 , wherein the first, second, and third electrodes are in parallel to one another.

11. The memory device of claim 8 , wherein the second and third electrodes are isolated from each other by at least the dielectric structure.

12. The memory device of claim 8 , further comprising:

a first transistor, wherein the second electrode is coupled to a drain feature or a source feature of the first transistor; and

a second transistor, wherein the third electrode is coupled to a drain feature or a source feature of the second transistor.

13. The memory device of claim 8 , wherein at least one of the first and second resistive material layers comprises a colossal magnetoresistance (CMR)-based material.

14. The memory device of claim 8 , wherein the first RRAM resistor further comprises:

a first capping layer comprising at least a portion that is coupled between the first electrode and the horizontal portion of the first resistive material layer; and

a second capping layer comprising at least a portion that is coupled between the vertical portion of the first resistive material layer and the second electrode.

15. The memory device of claim 8 , wherein the second RRAM resistor further comprises:

a first capping layer comprising at least a portion that is coupled between the first electrode and the horizontal portion of the second resistive material layer; and

a second capping layer comprising at least a portion that is coupled between the vertical portion of the second resistive material layer and the third electrode.

16. The memory device of claim 8 , wherein the first and second resistive material layers each presents a respective variable resistance value.

17. A method for forming a memory device, comprising:

providing a substrate including a lower electrode;

forming a plurality of dielectric structures laterally spaced from one another on the lower electrode;

forming a variable resistive material layer to overlay the lower electrode and each of the dielectric structures; and

polishing the variable resistive material layer to expose top surfaces of the dielectric structures and form a plurality of pairs of resistive material layers, wherein

each pair comprises first and second resistive material layers separated at two sides of one of the plurality of dielectric structures,

each of the first and second resistive material layers has a respective vertical portion that extends along a sidewall of the one of the plurality of dielectric structures, and

each of the first and second resistive material layers has a respective horizontal portion that is coupled to the lower electrode.

18. The method of claim 17 , further comprising:

forming a first capping layer over the plurality of dielectric structures and the substrate, wherein the variable resistive material layer is formed over the first capping layer; and

forming a second capping layer over the variable resistive material layer.

19. The method of claim 18 , further comprising:

patterning the first capping layer, the variable resistive material layer and the second capping layer;

forming an isolation layer over the substrate; and

forming a dielectric layer over the isolation layer.

20. The method of claim 19 , further comprising:

forming a plurality of recessed regions in the dielectric layer; and

forming respective upper electrodes in the plurality of recessed regions.