Semiconductor device and method of manufacturing the same

1. A semiconductor device, comprising:

semiconductor wires disposed over a channel region on a substrate;

a source/drain epitaxial layer in contact with the semiconductor wires which do not pass through the source/drain epitaxial layer;

a gate structure in the channel region, the gate structure comprising:

a gate dielectric layer disposed on and wrapping around the semiconductor wires in the channel region; and

a gate electrode layer disposed on the gate dielectric layer and wrapping around the semiconductor wires in the channel region; and

dielectric spacers disposed in recesses formed between the source/drain epitaxial layer and the gate structure at both ends of the channel region,

wherein each of the dielectric spacers has a curved face, which is a convex shape convex toward the source/drain epitaxial layer.

2. The semiconductor device of claim 1 , wherein the curved face convex toward the source/drain epitaxial layer is in contact with the gate dielectric layer.

3. The semiconductor device of claim 1 , wherein each of the dielectric spacers has curved faces, one of which is the convex shape convex toward the source/drain epitaxial layer and the other one of which is a concave shape concave toward the gate electrode in a cross section.

4. The semiconductor device of claim 1 wherein:

the gate structure further includes gate sidewall spacers, and

the dielectric spacers are made of different material than the gate sidewall spacers and include at least one of SiOC, SiOCN and SiCN.

5. The semiconductor device of claim 1 , wherein an interface between each of the dielectric spacers and the gate dielectric layer has a tapered shape having a smaller width toward the source/drain epitaxial layer.

6. The semiconductor device of claim 1 , wherein each of the dielectric spacers includes two layers.

7. The semiconductor device of claim 6 , wherein one of the two layers closer to the gate dielectric layer has a smaller thickness than the other one of the two layers.

8. A semiconductor device, comprising:

semiconductor wires made of Si and disposed over a channel region on a substrate;

a source/drain epitaxial layer in contact with the semiconductor wires which pass through the source/drain epitaxial layer, wherein the source/drain epitaxial layer includes SiP and wraps around the semiconductor wires;

a gate structure in the channel region, the gate structure comprising:

a gate dielectric layer disposed on and wrapping around the semiconductor wires in the channel region; and

a gate electrode layer disposed on the gate dielectric layer and wrapping around the semiconductor wires in the channel region; and

inner spacers disposed in recesses formed between the source/drain epitaxial layer and the gate structure at both ends of the channel region.

9. The semiconductor device of claim 8 , wherein:

each of the dielectric spacers has a curved face, and

the curved face is convex toward the source/drain epitaxial layer.

10. The semiconductor device of claim 8 , wherein each of the dielectric spacers has curved faces, one of which is the convex shape convex toward the source/drain epitaxial layer and the other one of which is a concave shape concave toward the gate electrode in a cross section.

11. The semiconductor device of claim 8 , wherein:

the gate structure further includes gate sidewall spacers, and

the dielectric spacers are made of different material than the gate sidewall spacers and include at least one of SiOC, SiOCN and SiCN.

12. The semiconductor device of claim 8 , wherein an interface between each of the dielectric spacers and the gate dielectric layer has a tapered shape having a smaller width toward the source/drain epitaxial layer.

13. The semiconductor device of claim 8 , wherein each of the dielectric spacers includes two layers.

14. The semiconductor device of claim 13 , wherein one of the two layers closer to the gate dielectric layer has a smaller thickness than the other one of the two layers.

15. A semiconductor device, comprising:

semiconductor wires disposed over a channel region on a substrate;

a source/drain epitaxial layer in contact with the semiconductor wires which do not pass through the source/drain epitaxial layer;

a gate structure in the channel region, the gate structure comprising:

a gate dielectric layer disposed on and wrapping around the semiconductor wires in the channel region;

a gate electrode layer disposed on the gate dielectric layer and wrapping around the semiconductor wires in the channel region; and

gate sidewall spacers disposed on opposing side faces of a part of the gate electrode layer above an uppermost one of the semiconductor wires; and

dielectric spacers disposed in recesses formed between the source/drain epitaxial layer and the gate structure,

wherein at least one of the dielectric spacers is located above the uppermost one of the semiconductor wires and below the gate sidewall spacers.

16. The semiconductor device of claim 15 , wherein:

each of the dielectric spacers has a curved face, and

the curved face is convex toward the source/drain epitaxial layer.

17. The semiconductor device of claim 15 , wherein each of the dielectric spacers has curved faces, one of which is a convex shape convex toward the source/drain epitaxial layer and the other one of which is a concave shape concave toward the gate electrode in a cross section.

18. The semiconductor device of claim 15 , wherein:

the dielectric spacers are made of different material than the gate sidewall spacers and include at least one of SiOC, SiOCN and SiCN.

19. The semiconductor device of claim 15 , wherein an interface between each of the dielectric spacers and the gate dielectric layer has a tapered shape having a smaller width toward the source/drain epitaxial layer.

20. The semiconductor device of claim 15 , wherein each of the dielectric spacers includes two layers.