IP Library › Granted Patent US 11,049,779
Granted Patent B2
US 11,049,779 · App. 16/558,180 · Granted Jun 29, 2021

Carrier for chip packaging and manufacturing method thereof

Inventor: Dyi-Chung Hu (Hsinchu, TW)
H01L23/13H01L21/566H01L23/481H01L23/5226H01L23/5283H01L24/09H01L24/17H01L2224/0231H01L2224/02373H01L2224/02381H01L2224/0401
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,049,779
App. No.
16/558,180
Granted
Jun 29, 2021
Kind
B2
Abstract

A carrier for a semiconductor chip mounting thereon and a manufacturing method thereof are provided. The carrier includes a fine redistribution structure, a plurality of conductive connectors, and an insulating layer. The fine redistribution structure has a first surface and a second surface opposite to each other, where the semiconductor chip is mounted on the first surface of the fine redistribution structure. The conductive connectors are disposed on the second surface of the fine redistribution structure and electrically coupled to the semiconductor chip through the fine redistribution structure. The insulating layer is disposed on the second surface of the fine redistribution structure to laterally cover the conductive connectors.

Claims (15)

1. A carrier for a semiconductor chip mounting thereon, comprising:

a fine redistribution structure having a first surface and a second surface opposite to each other, wherein the semiconductor chip is mounted on the first surface of the fine redistribution structure;

a plurality of conductive connectors disposed on the second surface of the fine redistribution structure and electrically coupled to the semiconductor chip through the fine redistribution structure, wherein each of the conductive connectors comprises a bump and a solder cap physically connected to the bump, and the bump is directly connected to the fine redistribution structure;

a top redistribution structure, directly connected to the solder cap of the conductive connectors;

an insulating layer disposed on the second surface of the fine redistribution structure to laterally cover the entire conductive connectors; and

a surface finishing layer disposed on the fine redistribution structure opposite to the conductive connectors, wherein the semiconductor chip is electrically connected the fine redistribution structure through the surface finishing layer.

2. The carrier according to claim 1 , wherein the insulating layer is made of an underfill material or a molding compound.

3. The carrier according to claim 1 , further comprising:

a bottom redistribution structure connected to the top redistribution structure and disposed opposite to the conductive connectors, wherein conductive elements of the top redistribution structure and the bottom redistribution structure are coarser than conductive elements of the fine redistribution structure, and a contact density of the top redistribution structure is denser than a contact density of the bottom redistribution structure.

4. The carrier according to claim 1 , further comprising:

a core layer having a top surface and a bottom surface opposing to each other, wherein the top redistribution structure is disposed on the top surface and the bottom redistribution structure is disposed on the bottom surface; and

a plurality of through core vias passing through the core layer and electrically connected to the top redistribution structure and the bottom redistribution structure.

5. The carrier according to claim 4 , wherein a dimension of each of the conductive connectors is less than a dimension of each of the through core vias.

6. The carrier according to claim 3 , wherein the insulating layer partially covers the conductive connectors, and each of the conductive connectors has a section protruding from the insulating layer and connected to the top redistribution structure.

7. The carrier according to claim 1 , wherein a height of one of the conductive connectors ranges from 20 μm to 200 μm.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 6, 2026
From: HU, DYI-CHUNG
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
Reel/Frame 075543/0215 →
Continuity (2)
Provisional Application 62744663 · Oct 12, 2018
Related Publication 20200118898A1 · Apr 16, 2020