Level shifting between interconnected chips having different voltage potentials
An input/output (I/O) interface of a die is disclosed. The I/O interface of the die includes a first region of a backside of the die. The I/O interface further includes a second region of the backside surface of the die positioned along at least a portion of a perimeter of the first region. The second region provides power and ground connections to the first region.
1. An input/output (I/O) interface of a die, the I/O interface of the die comprising:
a first region of a backside of the die; and
a second region of the backside of the die positioned along at least a portion of a perimeter of the first region, wherein the second region provides power and ground connections to the first region.
2. The I/O interface of the die of claim 1 , further comprising:
a plurality of microbumps bonded to a backside surface of the first region of the die.
3. The I/O interface of the die of claim 2 , further comprising:
a plurality of interconnects connected to the plurality of microbumps, the plurality of interconnects providing signal transmittance between the die and an additional die.
4. The I/O interface of the die of claim 1 , further comprising:
a plurality of controlled collapse chip connections (C 4 s ) bonded to a backside surface of the second region of the die.
5. The I/O interface of the die of claim 4 , wherein:
the plurality of C 4 s bonded to the backside surface of the second region of the die are arranged in at least one row along at least a portion of the perimeter of the first region.
6. The I/O interface of the die of claim 4 , further comprising:
a ground supply connected to a first portion of the plurality of C 4 s bonded to the backside surface of the second region of the die.
7. The I/O interface of the die of claim 4 , further comprising:
a first voltage supply connected to a second portion of the plurality of C 4 s bonded to the backside surface of the second region of the die.
8. The I/O interface of the die of claim 7 , wherein:
the first voltage supply is a dedicated voltage supply for powering circuits connected to the die.
9. The I/O interface of the die of claim 4 , further comprising:
a second voltage supply connected to a third portion of the plurality of C 4 s bonded to the backside surface of the second region of the die.
10. The I/O interface of the die of claim 9 , wherein:
the second voltage supply is a dedicated voltage supply for powering circuits located on an additional die that is interconnected to the die.
11. The I/O interface of the die of claim 1 , further comprising:
a power grid formed within at least two backside metal layers of the die and connected to the second region, wherein the power grid spans an area encompassed by the first region.
12. The I/O interface of the die of claim 1 , wherein:
an arrangement of at least a first voltage supply, a second voltage supply and a ground supply along at least a portion of the perimeter of the first region is dependent on respective power requirements of circuits located on the die.
13. The I/O interface of the die of claim 1 , wherein:
an arrangement of at least a first voltage supply, a second voltage supply and a ground supply along at least a portion of the perimeter of the first region is dependent on respective performance requirements of circuits located on the die.
14. A method of fabricating an input/output (I/O) interface of a die, the method comprising:
bonding a backside surface of a first region of the die to a corresponding topside surface of a first region of a package substrate via a plurality of microbumps; and
bonding a backside surface of a second region of the die positioned along at least a portion of a perimeter of the first region to a corresponding topside surface of a second region of a package substrate via a plurality of controlled collapse chip connections (C 4 s ), wherein:
the second region of the die delivers power to the first region of the die.
15. The method of claim 14 , further comprising:
arranging the plurality of C 4 s in at least one row along at least the portion of the perimeter of backend surface of the first region.
16. The method of claim 14 , further comprising:
routing a plurality of interconnects through a plurality of topside layers of the package substrate; and
connecting each interconnect in the plurality of interconnects to a single microbump in the plurality of microbumps.
17. The method of claim 15 , further comprising:
routing a ground supply rail through a first backside layer of the package substrate; and
connecting the ground supply rail to a first portion of the plurality of C 4 s bonding the second region of the backside surface of the die to the corresponding second region of the topside surface of the package substrate.
18. The method of claim 15 , further comprising:
routing a first voltage supply rail through a second backside layer of the package substrate; and
connecting the first voltage supply rail to a second portion of the plurality of C 4 s bonding the second region of the backside surface of the die to the corresponding second region of the topside surface of the package substrate.
19. The method of claim 15 , further comprising:
routing a second voltage supply rail through a third backside layer of the package substrate; and
connecting the second voltage supply rail to a third portion of the plurality of C 4 s bonding the second region of the backside surface of the die to the topside surface of the package substrate.
20. The method of claim 15 , further comprising:
forming a power grid within at least two backside metal layers of the die; and
connecting the power grid to the plurality of C 4 s bonding the second region of the backside surface of the die to the topside surface of the package substrate, wherein:
the power grid spans an area encompassed by the first region; and
the power grid delivers power to circuits located on the die.