Wafer to wafer high density interconnects
An integrated circuit package provides a high bandwidth interconnect between wafers using a very high density interconnect using a silicon bridge or a multi-layer flex between wafers. In some embodiments, more than one wafer may be mounted and connected with a rigid silicon bridge onto a common substrate. This common substrate can be matched, with respect to their coefficients of thermal expansion (CTE), to the silicon wafer. The CTE matched substrate can reduce the thermal mechanical stress on the wafers and the rigid silicon bridge interconnect. In some embodiments, a thinned silicon bridge is utilized to interconnect wafers which are mounted on separate glass substrates. The thinned bridge would allow for mechanical compliance between the wafers. In some embodiments, the wafers can be mounted onto separate glass substrates and attached with a fine pitch multi-layer flex structure which provides compliance between the wafers.
1 . A wafer scale system, comprising:
a plurality of wafers mounted on a substrate, wherein
the plurality of wafers comprises a first wafer and a second wafer,
the first wafer is adjacent to the second wafer, and
each of the first wafer and the second wafer comprises a plurality of die sites; and
a high density interconnect structure that comprises a plurality of signal wires, wherein each signal wire of the plurality of signal wires connects one or more die sites of the plurality of die sites of the first wafer to one or more die sites of the plurality of die sites of the second wafer.
2 . The wafer scale system of claim 1 , wherein the high density interconnect structure is a silicon bridge.
3 . The wafer scale system of claim 2 , wherein two or more wafers of the plurality of wafers are mounted on a shared substrate.
4 . The wafer scale system of claim 3 , wherein a coefficient of thermal expansion (CTE) of the two or more wafers is matched to a CTE of the substrate.
5 . The wafer scale system of claim 2 , wherein the silicon bridge includes two or more silicon bridges to connect the one or more die sites of the plurality of die sites of the first wafer to the one or more die sites of the plurality of die sites of the second wafer.
6 . The wafer scale system of claim 2 , wherein the silicon bridge provides a signal line pitch of less than about 1 micron.
7 . The wafer scale system of claim 1 , wherein
the high density interconnect structure is a thinned silicon bridge, and
the thinned silicon bridge provides a flexible interconnection between the one or more die sites of the plurality of die sites of the first wafer to the one or more die sites of the plurality of die sites of the second wafer.
8 . The wafer scale system of claim 7 , wherein each wafer of the plurality of wafers is independently mounted on a distinct and separate substrate.
9 . The wafer scale system of claim 7 , wherein the thinned silicon bridge provides a signal line pitch of less than 1 micron.
10 . The wafer scale system of claim 1 , wherein:
each wafer of the plurality of wafers is disposed in a respective wafer pod of a plurality of wafer pods,
a first wafer pod, of the plurality of wafer pods, includes a multilayer flex structure that terminates in a first connector of a plurality of connectors,
the first wafer pod is adjacent to a second wafer pod of the plurality of wafer pods,
the first connector is adjacent to a second connector of the plurality of connectors, and
the first connector is configured to connect with the second connector of the second wafer pod.
11 . The wafer scale system of claim 10 , wherein;
two or more multilayer flex structures connect the first wafer pod with the second wafer pod, and
the two or more multilayer flex structures include the multilayer flex structure.
12 . The wafer scale system of claim 10 , wherein each multilayer flex structure of two or more multilayer flex structures provides a signal line pitch of less than 10 microns.
13 . The wafer scale system of claim 1 , further comprising a cooling structure disposed between each wafer of the plurality of wafers and the substrate.
14 . The wafer scale system of claim 1 , wherein;
a frontside of one or more wafers of the plurality of wafers has through silicon vias, and
the one or more wafers are mounted onto the substrate.
15 . The wafer scale system of claim 14 , where a backside of the one or more wafers of the plurality of wafers includes redistribution layers to connect to the high density interconnect structure.
16 . A wafer scale system, comprising:
two or more wafers mounted on a substrate, wherein
the two or more wafers comprise a first wafer and a second wafer,
the first wafer is adjacent to the second wafer, and
each of the first wafer and the second wafer comprises a plurality of die sites; and
a silicon bridge that comprises a plurality of signal wires, wherein each signal wire of the plurality of signal wires connect one or more die sites of the plurality of die sites of the first wafer to one or more die sites of the plurality of die sites of the second wafer, wherein
the silicon bridge provides a signal line pitch of less than 1 micron.
17 . The wafer scale system of claim 16 , wherein:
the two or more wafers are mounted on a shared substrate, and
a coefficient of thermal expansion (CTE) of the two or more wafers is matched to a CTE of the shared substrate.
18 . The wafer scale system of claim 16 , wherein:
the silicon bridge is a thinned silicon bridge,
the thinned silicon bridge provides a flexible interconnection between the one or more die sites of the plurality of die sites of the first wafer and the one or more die sites of the plurality of die sites of the second wafer, and
each wafer of the two or more wafers is independently mounted on a distinct and separate substrate.
19 . A wafer scale system, comprising:
two or more wafers each packaged in a first wafer pod of a plurality of wafer pods, wherein
the two or more wafers comprise a first wafer and a second wafer,
the first wafer is adjacent to the second wafer, and
each of the first wafer and the second wafer comprises a plurality of die sites;
a silicon bridge that comprises a plurality of signal wires, wherein each signal wire of the plurality of signal wires connect one or more die sites of the plurality of die sites of the first wafer to one or more die sites of the plurality of die sites of the second wafer; and
a multilayer flex structure connected to each wafer of the two or more wafers, wherein
the multilayer flex structure terminates in a first connector of a plurality of connectors, wherein
the first wafer pod is adjacent to a second wafer pod of the plurality of wafer pods,
the first connector is adjacent to a second connector of the plurality of connectors,
the first connector is configured to connect with the second connector of the second wafer pod, and
the multilayer flex structure provides a signal line pitch of less than 10 micron.
20 . The wafer scale system of claim 19 , wherein:
each wafer pod, of the plurality of wafer pods, includes one or more connectors of the plurality of connectors at each face,
the one or more connectors connect the first wafer pod to four wafer pods of the plurality of wafer pods, and
each wafer pod of the four wafer pods is adjacent to the first wafer pod.