IP Library Granted Patent US 11,056,346
Granted Patent B2
US 11,056,346 · App. 16/999,513 · Granted Jul 6, 2021

Wafer processing method

Inventors: Hideyuki Sandoh (Tokyo, JP); Ichiro Yamahata (Tokyo, JP); Tomotaka Tabuchi (Tokyo, JP)
Assignee: DISCO CORPORATION
H01L21/304H01L21/3065
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,056,346
App. No.
16/999,513
Granted
Jul 6, 2021
Kind
B2
Abstract

There is provided a wafer processing method for reducing a thickness of a wafer. The wafer has a front side and a back side opposite to the front side. The wafer has a device area where a plurality of devices are formed on the front side and a peripheral marginal area including a curved peripheral edge. A protective layer for covering the plural devices are formed on the front side in the device area. The wafer processing method includes a plasma etching step of supplying an etching gas in a plasma condition to the front side of the wafer by using the protective layer as a mask, thereby removing the peripheral marginal area including the curved peripheral edge, a protective member attaching step of attaching a protective member to the front side of the wafer, and a grinding step of grinding the back side of the wafer.

Claims (9)

1. A wafer processing method for reducing a thickness of a wafer to a predetermined thickness, the wafer having a front side and a back side opposite to the front side, the wafer having a device area where a plurality of devices are formed on the front side and a peripheral marginal area surrounding the device area and including a curved peripheral edge, a protective layer for covering the plurality of devices being formed on the front side in the device area, the protective layer being not formed in the peripheral marginal area, the wafer processing method comprising:

a plasma etching step of supplying an etching gas in a plasma condition to the front side of the wafer by using the protective layer as a mask, thereby removing the peripheral marginal area including the curved peripheral edge such that a depth of an etched portion of the peripheral marginal area becomes larger than the predetermined thickness;

a protective member attaching step of attaching a protective member to the front side of the wafer after performing the plasma etching step; and

a grinding step of holding the wafer through the protective member on a chuck table included in a grinding apparatus and then grinding the back side of the wafer to thereby reduce the thickness of the wafer to the predetermined thickness.

2. The wafer processing method according to claim 1 , wherein

the protective layer includes a passivation film or a photoresist film formed on the front side of the wafer in a step of forming the plurality of devices.

3. The wafer processing method according to claim 1 , wherein

the protective layer is formed such that an interdevice area between any adjacent ones of the plurality of devices on the front side of the wafer is exposed,

the plasma etching step including the step of supplying the etching gas in the plasma condition to the front side of the wafer by using the protective layer as the mask, thereby removing the peripheral marginal area and also forming a groove along the interdevice area in the device area on the front side of the wafer, the groove having a depth larger than the predetermined thickness.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2020
From: SANDOH, HIDEYUKI; YAMAHATA, ICHIRO; TABUCHI, TOMOTAKA
To: DISCO CORPORATION
Reel/Frame 053562/0652 →
Priority Claims (1)
JP JP2019-151803 · Aug 22, 2019 · national
Continuity (1)
Related Publication 20210057225A1 · Feb 25, 2021
Cited By (1)
US 12,311,470