Epitaxial structures of semiconductor devices that are independent of local pattern density

1. A method of forming a semiconductor device comprising:

providing active gate structures over an active region;

forming a hard mask segment on the active region positioned between a first active gate structure and a second active gate structure, the second active gate structure being immediately adjacent to the first active gate structure;

forming cavities in the active region between the first and second active gate structures using the active gate structures and the hard mask segment as masking features, wherein each cavity is substantially uniform in size and the cavities separated by an active region segment therebetween, the active region segment having a pre-determined width that defines the widths of the cavities; and

growing epitaxial material in the cavities to form epitaxial structures that are substantially uniform in size in the active region.

2. The method of claim 1 , wherein forming the hard mask segment further comprises:

depositing a hard mask layer over the active gate structures and the active region;

depositing a patterning layer over the hard mask layer;

forming openings in the patterning layer to expose portions of the hard mask layer; and

removing the exposed portions of the hard mask layer to form the hard mask segment.

3. The method of claim 1 wherein the hard mask segment is formed of silicon nitride.

4. The method of claim 1 further comprises depositing an electrically conductive material over the epitaxial structures, wherein the electrically conductive material forms source/drain contacts that connect the epitaxial structures of the semiconductor device.

5. The method of claim 1 wherein the cavities in the active region include a first cavity formed between the first active gate structure and the hard mask segment and a second cavity formed between the hard mask segment and the second active gate structure.

6. The method of claim 5 wherein the hard mask segment has a pre-determined width that defines the widths of the first and second cavities in the active region to be substantially equal to the minimum gate-to-gate spacing of the semiconductor device.

7. The method of claim 5 further comprising forming a doped region under the hard mask segment using an implantation process to electrically connect the epitaxial structures in the first and second cavities in the active region.

8. A method of forming a semiconductor device comprising:

providing a first active gate structure and a second active gate structure over an active region, the second active gate structure being immediately adjacent to the first active gate structure;

forming a hard mask layer over the first active gate structure, the second active gate structure and the active region;

removing portions of the hard mask layer to form a hard mask segment and exposing a first portion of the active region between the first active gate structure and the hard mask segment and a second portion of the active region between the hard mask segment and the second active gate structure;

forming cavities in the exposed first and second portions of the active region, wherein each cavity is substantially uniform in size and the cavities separated by an active region segment therebetween, the active region segment having a pre-determined width that defines the widths of the cavities; and

growing epitaxial material in the cavities to form epitaxial structures that are substantially uniform in size in the active region.

9. The method of claim 8 wherein the hard mask segment is formed by a lithographic process to expose portions of the hard mask layer using a patterning layer and a dry etch process to remove the exposed portions of the hard mask layer to form the hard mask segment.

10. The method of claim 8 wherein the hard mask segment has a pre-determined width that defines the widths of the cavities in the active region.

11. The method of claim 8 wherein the cavities in the active region are formed using the first active gate structure, the second active gate structure and the hard mask segment as masking features.

12. The method of claim 11 wherein the cavities of the active region are formed by a reactive ion etch process.

13. The method of claim 8 wherein the epitaxial structures are connected by an electrically conductive material.

14. The method of claim 13 wherein the electrically conductive material forms source/drain contacts of the semiconductor device.

15. A semiconductor device comprising:

a first active gate structure and a second active gate structure over an active region, the second active gate structure being immediately adjacent to the first active gate structure;

at least two epitaxial structures therebetween the first and second active gate structures, wherein the two epitaxial structures are separated by an active region segment, the active region segment having a pre-determined width that defines the widths of the epitaxial structures; and

the at least two epitaxial structures are substantially uniform in size.

16. The semiconductor device of claim 15 , wherein the active region segment comprises dopants.

17. The semiconductor device of claim 15 , further comprises a dielectric layer over the active region segment.

18. The semiconductor device of claim 15 wherein the at least two epitaxial structures are connected by an electrically conductive material.

19. The semiconductor device of claim 18 wherein the electrically conductive material forms source/drain contacts.

20. The semiconductor device of claim 15 , wherein the at least two epitaxial structures have a width substantially equal to the minimum gate-to-gate spacing of the semiconductor device.