Silicon substrate modification to enable formation of thin, relaxed, germanium-based layer

1. An integrated circuit (IC) comprising:

a substrate that includes silicon;

a first layer on the substrate and including a first monocrystalline semiconductor material, the first layer having a plurality of defects, wherein at least some of the plurality of defects terminate in the substrate;

a second layer on the first layer and including a second monocrystalline semiconductor material that includes germanium, the second layer having a maximum vertical thickness of at most 400 nanometers (nm);

a strained channel structure above the first layer;

a gate structure at least above the channel structure;

a source region adjacent the channel structure; and

a drain region adjacent the channel structure, such that the channel structure is laterally between the source region and the drain region.

2. The IC of claim 1 , wherein the substrate is monocrystalline silicon.

3. The IC of claim 1 , wherein the first layer is native to the substrate.

4. The IC of claim 1 , wherein the first layer is not native to the substrate and the first monocrystalline semiconductor material includes germanium.

5. The IC of claim 1 , wherein the first layer includes at least one of silicon, carbon, germanium, hydrogen, helium, phosphorous, boron, arsenic, antimony, tin, indium, gallium, or argon.

6. The IC of claim 1 , wherein the first layer has a maximum thickness of at most 50 nm.

7. The IC of claim 1 , wherein the second monocrystalline semiconductor material further includes at least one of silicon, tin, or carbon.

8. The IC of claim 1 , wherein the second monocrystalline semiconductor material includes at least 30 percent germanium concentration by atomic percentage.

9. The IC of claim 1 , wherein the second layer has a top surface including a dislocation density of at most 1E7 per square centimeter.

10. The IC of claim 1 , wherein a top surface of the second layer has a lattice constant that is closer to the bulk lattice constant of the second monocrystalline semiconductor material than the bulk lattice constant of silicon.

11. The IC of claim 1 , wherein the channel structure is at least one of in or on the second layer.

12. The IC of claim 1 , wherein the channel structure includes a third monocrystalline semiconductor material that is compositionally different than the second monocrystalline semiconductor material.

13. The IC of claim 12 , wherein the third monocrystalline semiconductor material is one of n-type and p-type doped and the second monocrystalline semiconductor material is the other of n-type and p-type doped.

14. The IC of claim 1 , wherein the channel structure includes at least a portion of the second layer.

15. The IC of claim 1 , wherein the channel structure is a first channel structure, the IC further comprising a complementary metal-oxide-semiconductor (CMOS) circuit including a first transistor and a second transistor, the first transistor including the first channel structure, and the second transistor including a second channel structure also above the first layer, wherein one of the first and second transistors is an n-channel transistor and the other of the first and second transistors is a p-channel transistor, wherein the n-channel transistor includes tensile strain in the corresponding channel structure and the p-channel transistor includes compressive strain in the corresponding channel structure.

16. An integrated circuit (IC) comprising:

a bulk silicon substrate;

a layer above the substrate and including monocrystalline semiconductor material that includes germanium, the layer having a maximum vertical thickness of at most 300 nanometers (nm), the layer further having a top surface including a dislocation density of at most 1E7 per square centimeter;

an intervening layer between the layer and the substrate, the intervening layer including monocrystalline semiconductor material and having a maximum thickness of at most 50 nm;

a channel region above the intervening layer;

a gate structure at least above the channel region;

a source region adjacent the channel region; and

a drain region adjacent the channel region.

17. The IC of claim 16 , wherein the intervening layer is native to the substrate.

18. The IC of claim 16 , wherein the intervening layer is not native to the substrate, such that a distinct interface exists between the intervening layer and the substrate.

19. An integrated circuit (IC) comprising:

a substrate of monocrystalline silicon;

a layer on the substrate and including monocrystalline semiconductor material that includes silicon and germanium, the germanium being at a concentration of less than 35 atomic percent, the layer having a maximum vertical thickness of less than 250 nanometers (nm), wherein an interface between the layer and the substrate includes defects, and the defects terminate within the substrate and/or in a bottom portion of the layer, such that none of the defects run to a top surface of the layer;

a PMOS device on the layer and having a first gate structure on at least top and side surfaces of a compressively strained region comprising monocrystalline semiconductor material; and

an NMOS device on the layer and having a second gate structure on at least top and side surfaces of a tensile strained region comprising monocrystalline semiconductor material.

20. The IC of claim 19 , wherein the top surface of the layer has a dislocation density of 1E7 per square centimeter or less, and the layer has greater than 80% relaxation.