Method for forming chip package structure
A method for forming a chip package structure is provided. The method includes forming a conductive pillar over a redistribution structure. The method includes bonding a chip to the redistribution structure. The method includes forming a molding layer over the redistribution structure. The molding layer surrounds the conductive pillar and the chip, and the conductive pillar passes through the molding layer. The method includes forming a cap layer over the molding layer and the conductive pillar. The cap layer has a through hole exposing the conductive pillar, and the cap layer includes fibers. The method includes forming a conductive via structure in the through hole. The conductive via structure is connected to the conductive pillar.
1. A method for forming a chip package structure, comprising:
bonding a first chip to a substrate;
bonding a second chip to a redistribution structure;
bonding the substrate to the redistribution structure, wherein the first chip and the second chip are between the substrate and the redistribution structure, and a distance between a first surface of the first chip and a nearest insulating layer of the redistribution structure is less than a distance between a second surface of the second chip and the nearest insulating layer of the redistribution structure, wherein the first surface of the first chip faces the redistribution structure, and the second surface of the second chip faces away from the redistribution structure; and
forming a first molding layer between the substrate and the redistribution structure to encapsulate the first chip and the second chip.
2. The method for forming the chip package structure as claimed in claim 1 , further comprising:
bonding a third chip to a surface of the substrate after bonding the substrate to the redistribution structure, wherein the surface faces away from the redistribution structure.
3. The method for forming the chip package structure as claimed in claim 2 , further comprising:
forming a second molding layer over the surface of the substrate, wherein the second molding layer surrounds the third chip.
4. The method for forming the chip package structure as claimed in claim 3 , wherein a first top surface of the second molding layer is substantially coplanar with a second top surface of the third chip.
5. The method for forming the chip package structure as claimed in claim 1 , wherein the substrate is bonded to the redistribution structure through a conductive bump.
6. The method for forming the chip package structure as claimed in claim 5 , further comprising:
forming a pillar structure over the redistribution structure before bonding the substrate to the redistribution structure, wherein the pillar structure penetrates into the conductive bump after bonding the substrate to the redistribution structure.
7. The method for forming the chip package structure as claimed in claim 1 , wherein a portion of the first molding layer is between a first sidewall of the first chip and a second sidewall of the second chip.
8. The method for forming the chip package structure as claimed in claim 1 , further comprising:
forming an adhesive layer over the first chip before bonding the substrate to the redistribution structure, wherein the first chip is bonded to the redistribution structure through the adhesive layer during bonding the substrate to the redistribution structure.
9. The method for forming the chip package structure as claimed in claim 1 , wherein the substrate comprises fibers.
10. A method for forming a chip package structure, comprising:
bonding a first chip on a first side of a substrate;
bonding a second chip to front side of a redistribution structure;
bonding the substrate to the redistribution structure, wherein the first side of the substrate faces the front side of the redistribution structure, and the first chip has no portion overlapping the second chip in a vertical direction of the substrate; and
forming a molding layer to cover the first chip and the second chip.
11. The method for forming the chip package structure as claimed in claim 10 , wherein the substrate and the redistribution structure are bonded by conductive bumps, and the first chip and the second chip are disposed between the conductive bumps.
12. The method for forming the chip package structure as claimed in claim 11 , further comprising forming a pillar structure over the redistribution structure before bonding the substrate to the redistribution structure, wherein the pillar structure penetrates into the conductive bump after bonding the substrate to the redistribution structure.
13. The method for forming the chip package structure as claimed in claim 10 , wherein a first gap is formed between the first chip and the redistribution structure, a second gap is formed between the second chip and the substrate.
14. The method for forming the chip package structure as claimed in claim 10 , further comprising forming a third chip and a fourth chip on a second side of the substrate, wherein the first side is opposite from the second side.
15. The method for forming the chip package structure as claimed in claim 14 , wherein a top surface of the third chip is exposed from the molding layer, and a top surface of the fourth chip is covered by the molding layer.
16. A method for forming a chip package structure, comprising:
bonding a first chip to a first side of a substrate, wherein the substrate comprises a core layer and insulating layers covering the core layer, and the core layer comprises fiber;
bonding a second chip to a redistribution structure;
bonding the substrate to the redistribution structure, wherein the first chip and the second chip are between the substrate and the redistribution structure, and a sidewall of the first chip overlaps a sidewall of the second chip in a horizontal direction of the substrate that is parallel to a top surface of the substrate, and the top surface of the substrate faces the redistribution structure; and
forming a first molding layer between the substrate and the redistribution structure.
17. The method for forming the chip package structure as claimed in claim 16 , further comprising forming a third chip and a fourth chip on a second side of the substrate, wherein the first side and the second side are opposite, and the height of the third chip is different from the height of the fourth chip.
18. The method for forming the chip package structure as claimed in claim 16 , wherein the molding layer further forms on a sidewall of the substrate.
19. The method for forming the chip package structure as claimed in claim 18 , wherein the sidewall of the core layer is in direct contact with the molding layer.
20. The method for forming the chip package structure as claimed in claim 16 , wherein in a cross-sectional view, an extension of the sidewall of the first chip does not pass through the second chip.