Metal frame, dummy wafer, semiconductor device, electronic device, and method of manufacturing semiconductor device
A metal frame that is used in a dummy wafer in which chip-like semiconductor elements and a rewiring layer are integrated. A plurality of openings in which the chip-like semiconductor elements are disposed are formed in the metal plate, and a lattice structure is formed with the frames that are the portions between adjacent openings of the plurality of openings. Of the frames forming the lattice structure, the frames located in dicing areas of the dummy wafer are arranged in a discontinuous manner.
1. A metal frame, comprising:
a plurality of openings, wherein each opening of the plurality of openings includes a plurality of chip-like semiconductor elements; and
a lattice structure including a plurality of frames, wherein
each frame of the plurality of frames is between adjacent openings of the plurality of openings,
the plurality of frames includes a set of frames in a dicing area of a dummy wafer, and
frames of the set of frames are in a discontinuous arrangement on a dicing length of the dicing area.
2. The metal frame according to claim 1 , wherein an opening of the plurality of openings includes at least one singulated region of the dummy wafer.
3. The metal frame according to claim 1 , wherein the plurality of openings includes an opening in which a singulated region of the dummy wafer is absent.
4. The metal frame according to claim 3 , wherein
the plurality of frames includes a specific frame at a position that deviates from the dicing area, and
the specific frame extends longitudinally in the singulated region.
5. The metal frame according to claim 1 , further comprising a material that is one of copper, a copper alloy, or an iron alloy.
6. The metal frame according to claim 1 , further comprising a metal.
7. The metal frame according to claim 1 , further comprising a metal material layer at a portion of the metal frame corresponding to the plurality of frames.
8. A dummy wafer, comprising:
a metal frame that includes:
a plurality of openings, wherein each opening of the plurality of openings includes a plurality of chip-like semiconductor elements; and
a lattice structure that includes a plurality of frames, wherein
each frame of the plurality of frames is between adjacent openings of the plurality of openings,
the plurality of frames includes a set of frames in a dicing area of the dummy wafer, and
frames of the set of frames are in a discontinuous arrangement on a dicing length of the dicing area; and
a rewiring layer integrated with the plurality of chip-like semiconductor elements.
9. A semiconductor device, comprising:
a specific frame of a metal frame of a dummy wafer;
at least one chip-like semiconductor element of a plurality of chip-like semiconductor elements, wherein the metal frame includes:
a plurality of openings, wherein each opening of the plurality of openings includes the plurality of chip-like semiconductor elements; and
a lattice structure that includes a plurality of frames, wherein
the plurality of frames includes the specific frame,
each frame of the plurality of frames is between adjacent openings of the plurality of openings,
the plurality of frames includes a set of frames in a dicing area of the dummy wafer, and
frames of the set of frames are in a discontinuous arrangement on a dicing length of the dicing area; and
a rewiring layer integrated with the at least one chip-like semiconductor element.
10. An electronic device, comprising:
a semiconductor device that includes:
a specific frame of a dummy wafer;
at least one chip-like semiconductor element of a plurality of chip-like semiconductor elements, wherein the dummy wafer includes:
a metal frame that includes:
a plurality of openings, wherein each opening of the plurality of openings includes the plurality of chip-like semiconductor elements; and
a lattice structure that includes a plurality of frames, wherein
the plurality of frames includes the specific frame,
each frame of the plurality of frames is between adjacent openings of the plurality of openings,
the plurality of frames includes a set of frames in a dicing area of the dummy wafer, and
frames of the set of frames are in a discontinuous arrangement on a dicing length of the dicing area; and
a rewiring layer integrated with the at least one chip-like semiconductor element.
11. A method of manufacturing a semiconductor device, comprising:
disposing a metal frame and a plurality of chip-like semiconductor elements on a support, wherein the metal frame includes:
a lattice structure including a plurality of frames; and
a plurality of openings, wherein
each frame of the plurality of frames is between adjacent openings of the plurality of openings,
the plurality of frames includes a set of frames in a dicing area of a dummy wafer,
frames of the set of frames are in a discontinuous arrangement on a dicing length of the dicing area, and
each opening of the plurality of openings includes the plurality of chip-like semiconductor elements;
forming a sealing layer on an entire surface of the support including the metal frame that is on the support and the plurality of chip-like semiconductor elements that is on the support;
detaching the sealing layer from the support; and
forming a rewiring layer on a release surface side of the sealing layer.
12. The method of manufacturing the semiconductor device according to claim 11 , further comprising dicing the dummy wafer into a plurality of pieces to obtain the semiconductor device, wherein the semiconductor device includes at least one chip-like semiconductor element of the plurality of chip-like semiconductor elements and the rewiring layer.
13. The method of manufacturing the semiconductor device according to claim 11 , wherein the metal frame disposed on the support includes a metal material layer.
14. The method of manufacturing the semiconductor device according to claim 13 , further comprising forming the metal material layer by a plating process.
15. A method of manufacturing a semiconductor device, comprising:
forming a rewiring layer on a support;
forming a metal frame on the rewiring layer, wherein the metal frame includes:
a lattice structure including a plurality of frames; and
a plurality of openings, wherein
each frame of the plurality of frames is between adjacent openings of the plurality of openings,
the plurality of frames includes a set of frames in a dicing area of a dummy wafer, and
frames of the set of frames are in a discontinuous arrangement on a dicing length of the dicing area;
disposing a plurality of chip-like semiconductor elements on the rewiring layer in each opening of the plurality of openings in the metal frame;
forming a sealing layer on an entire surface of the rewiring layer, the metal frame that is on the rewiring layer, and the plurality of chip-like semiconductor elements that is on the rewiring layer; and
detaching the rewiring layer from the support.
16. The method of manufacturing the semiconductor device according to claim 15 , further comprising dicing the dummy wafer into a plurality of pieces to obtain the semiconductor device, wherein the semiconductor device includes the plurality of chip-like semiconductor elements and the rewiring layer.
17. The method of manufacturing the semiconductor device according to claim 15 , wherein the metal frame disposed on the support includes a metal material layer.
18. The method of manufacturing the semiconductor device according to claim 17 , further comprising forming the metal material layer by a plating process.