Fan-out package with controllable standoff

1. A method comprising:

forming an interposer comprising:

forming a rigid dielectric layer, wherein the rigid dielectric layer comprises a first surface and a second surface opposing to each other and parallel to each other, and the rigid dielectric layer comprises a first portion, and a second portion and a third portion on opposing sides of the first portion, wherein each of the first portion, the second portion, and the third portion extends from the first surface to the second surface; and

removing portions of the rigid dielectric layer wherein the removing comprises removing entireties of the second portion and the third portion;

bonding a package component to an interconnect structure to form a fan-out package;

bonding the interposer to the fan-out package, wherein after the bonding, a bottom surface of the rigid dielectric layer contacts a top surface of the package component; and

performing a die-saw on the interconnect structure.

2. The method of claim 1 further comprising forming the interconnect structure on a carrier, with the package component bonded to the interconnect structure when the interconnect structure is located on the carrier.

3. The method of claim 1 , wherein the forming the interposer further comprises:

forming a metal feature, with the rigid dielectric layer being formed to embed the metal feature therein; and

performing a planarization process to level a surface of the metal feature with a surface of the rigid dielectric layer.

4. The method of claim 1 , wherein the forming the rigid dielectric layer comprises embedding a conductive feature in the rigid dielectric layer, and wherein after the interposer is bonded to the fan-out package, the conductive feature is electrically floating.

5. The method of claim 4 , wherein the conductive feature is a through-feature that penetrates through the rigid dielectric layer.

6. The method of claim 1 , wherein the package component comprises a device die comprising a semiconductor substrate and a metal layer physically contacting the semiconductor substrate, and after the bonding the interposer to the interconnect structure, a solder region is bonded to the metal layer.

7. A method comprising:

forming an interposer comprising:

plating a metal spacer over a first carrier;

forming a dielectric layer to embed the metal spacer therein;

forming a substrate over the dielectric layer;

forming through-vias penetrating through the substrate;

forming a first plurality of redistribution lines over and electrically coupling to the through-vias;

removing the first carrier to reveal the dielectric layer; and

patterning the dielectric layer to remove a first portion of the dielectric layer, wherein a second portion of the dielectric layer remains;

forming an interconnect structure over a second carrier;

bonding a package component to the interconnect structure; and

bonding the interposer to the interconnect structure, wherein the metal spacer and the second portion of the dielectric layer space the package component from the substrate.

8. The method of claim 7 , wherein the forming the interposer further comprises forming a solder region on the metal spacer.

9. The method of claim 8 , wherein the package component comprises:

a semiconductor substrate; and

a blanket metal layer over the semiconductor substrate, wherein when the interposer is bonded to the interconnect structure, the solder region is simultaneously bonded to the blanket metal layer.

10. The method of claim 7 further comprising:

forming a plurality of metal pads on the dielectric layer; and

forming a plurality of metal pillars on the interposer, wherein the through-vias and the plurality of metal pillars are on opposite surfaces of the plurality of metal pads; and

forming a plurality of solder regions, each on one of the plurality of metal pillars.

11. The method of claim 7 further comprising:

forming a plurality of metal pads on the dielectric layer; and

forming a plurality of solder regions on the interposer, wherein the through-vias and the plurality of solder regions are on opposite surfaces of the plurality of metal pads.

12. The method of claim 7 , wherein the forming the substrate comprises laminating a film.

13. The method of claim 7 , wherein the forming the dielectric layer to embed the metal spacer comprises:

laminating a dielectric film on the metal spacer; and

planarizing the metal spacer and the dielectric film.

14. A method comprising:

forming an interposer comprising:

forming metal spacers over a carrier;

forming a substrate over the metal spacers;

forming through-vias, wherein after the substrate and the through-vias are both formed, the through-vias penetrate through the substrate;

removing the carrier; and

forming metal pillars underlying the substrate, wherein the metal pillars are electrically connected to the through-vias; and

bonding the interposer to a package, wherein the metal pillars are bonded to metal pads in the package through a solder region, and the metal spacers are in contact with a top surface of a device die in the package.

15. The method of claim 14 , wherein the metal spacers are in a dielectric layer, and after the bonding, the dielectric layer is in contact with the top surface of the device die.

16. The method of claim 15 further comprising:

forming a blanket layer; and

etching the blanket layer to form the dielectric layer.

17. The method of claim 16 , wherein the dielectric layer is between opposing ones of the metal pillars.

18. The method of claim 14 , wherein the through-vias, the metal spacers, and the substrate are formed over the carrier.

19. The method of claim 18 further comprising, after the substrate is formed, de-bonding the carrier.

20. The method of claim 6 , wherein the first portion of the rigid dielectric layer have first opposing edges laterally recessed from second opposing edges of the device die.