Interposer and semiconductor package including the same

1. An interposer comprising:

a base substrate;

an interconnection structure arranged on a top surface of the base substrate and comprising a metal interconnection pattern;

a connection pad arranged on the interconnection structure and electrically connected to the metal interconnection pattern of the interconnection structure;

an upper passivation layer arranged on the interconnection structure and having compressive stress, a bottom region of the upper passivation layer including a silicon oxide layer, and a bottom surface of the upper passivation layer being coplanar with a bottom surface of the connection pad;

a lower passivation layer arranged on a bottom surface of the base substrate and having compressive stress that is less than the compressive stress of the upper passivation layer;

a lower conductive layer on the lower passivation layer; and

a through electrode penetrating the base substrate and the lower passivation layer and electrically connecting the lower conductive layer to the metal interconnection pattern of the interconnection structure.

2. The interposer of claim 1 ,

wherein the compressive stress of the upper passivation layer is between about 150 MPa and about 250 MPa, and

the compressive stress of the lower passivation layer is between about 100 MPa and about 200 MPa.

3. The interposer of claim 1 ,

wherein a thickness of the lower passivation layer is greater than a thickness of the upper passivation layer.

4. The interposer of claim 3 ,

wherein the thickness of the upper passivation layer is between about 1 μm and about 2 μm, and

the thickness of the lower passivation layer is between about 2 μm and about 3 μm.

5. The interposer of claim 1 ,

wherein the lower passivation layer includes a silicon oxide layer,

wherein each of the upper passivation layer and the lower passivation layer comprise a silicon nitride layer, and

wherein the silicon oxide layer of the upper passivation layer and the silicon oxide layer of the lower passivation layer are between the silicon nitride layer of the upper passivation layer and the silicon nitride layer of the lower passivation layer.

6. The interposer of claim 1 ,

wherein the upper passivation layer comprises a first layer on the interconnection structure and comprising the silicon oxide layer, and

wherein the upper passivation layer comprises a second layer arranged on the first layer and comprising a silicon nitride.

7. The interposer of claim 1 ,

wherein the lower passivation layer comprises a first layer arranged on the bottom surface of the base substrate and comprising a silicon oxide and a second layer arranged on the first layer and comprising a silicon nitride.

8. The interposer of claim 1 ,

further comprising a connection pad arranged on the interconnection structure and electrically connected to the metal interconnection pattern of the interconnection structure,

wherein the upper passivation layer covers a portion of the connection pad.

9. The interposer of claim 8 ,

wherein a thickness of the upper passivation layer is equal to a thickness of the connection pad.

10. The interposer of claim 8 ,

wherein a thickness of the upper passivation layer is greater than a thickness of the connection pad.

11. The interposer of claim 8 ,

wherein the upper passivation layer comprises a bottom surface facing the interconnection structure and a top surface opposite to the bottom surface of the upper passivation layer, and

the top surface of the upper passivation layer is flat.

12. An interposer comprising:

a base substrate;

an interconnection structure arranged on a top surface of the base substrate and comprising a metal interconnection pattern;

an upper passivation layer covering a top surface of the interconnection structure and having compressive stress;

a connection pad arranged on the top surface of the interconnection structure and electrically connected to the metal interconnection pattern of the interconnection structure, a bottom surface of the connection pad being coplanar with a bottom surface of the upper passivation layer; and

a lower passivation layer covering a bottom surface of the base substrate and having compressive stress,

wherein a thickness of the upper passivation layer is greater than or equal to a thickness of the connection pad,

wherein each of the upper passivation layer and the lower passivation layer comprises a multilayer structure comprising a silicon oxide layer and a silicon nitride layer, and

wherein the silicon oxide layer of the upper passivation layer is on the top surface of the interconnection structure, and the silicon nitride layer of the upper passivation layer is on the silicon oxide layer of the upper passivation layer.

13. The interposer of claim 12 ,

wherein the upper passivation layer comprises a planarized top surface.

14. The interposer of claim 13 ,

wherein the thickness of the upper passivation layer is equal to the thickness of the connection pad, and the top surface of the upper passivation layer is coplanar with a top surface of the connection pad.

15. The interposer of claim 13 ,

wherein the thickness of the upper passivation layer is greater than the thickness of the connection pad, and

the top surface of the upper passivation layer is at a higher level than a top surface of the connection pad.

16. The interposer of claim 12 ,

wherein the compressive stress of the upper passivation layer is greater than the compressive stress of the lower passivation layer.

17. A semiconductor package comprising: an interposer; and at least one semiconductor chip arranged on the interposer,

wherein the interposer comprises:

a base substrate;

an interconnection structure arranged on a top surface of the base substrate and comprising a metal interconnection pattern;

a connection pad arranged on the interconnection structure and electrically connected to the metal interconnection pattern of the interconnection structure;

an upper passivation layer arranged on the interconnection structure, covering a portion of the connection pad, and having compressive stress;

a lower passivation layer arranged on a bottom surface of the base substrate and having compressive stress;

a lower conductive layer on the lower passivation layer; and

a through electrode penetrating the base substrate and the lower passivation layer and electrically connecting the lower conductive layer to the metal interconnection pattern of the interconnection structure,

wherein a thickness of the lower passivation layer is greater than a thickness of the upper passivation layer.

18. The semiconductor package of claim 17 ,

wherein the compressive stress of the upper passivation layer is greater than the compressive stress of the lower passivation layer.

19. The semiconductor package of claim 17 ,

wherein the upper passivation layer comprises a silicon nitride layer and a silicon oxide layer,

the silicon oxide layer and the silicon nitride layer of the upper passivation layer are sequentially stacked on the interconnection structure,

the lower passivation layer comprises a silicon oxide layer and a silicon nitride layer sequentially stacked on the bottom surface of the base substrate, and

wherein the silicon oxide layer of the upper passivation layer and the silicon oxide layer of the lower passivation layer are between the silicon nitride layer of the upper passivation layer and the silicon nitride layer of the lower passivation layer.