Method for forming semiconductor structure
A method for forming a semiconductor structure is provided. The method includes forming a contact feature over an insulating layer, forming a first passivation layer over the contact feature, and etching the first passivation layer to form a trench exposing the contact feature. The method also includes forming an oxide layer over the contact feature and the first passivation layer and in the trench, forming a first non-conductive structure over the oxide layer, and patterning the first non-conductive structure to form a gap. The method further includes filling a conductive material in the gap to form a first conductive feature. The first non-conductive structure and the first conductive feature form a first bonding structure. The method further includes attaching a carrier substrate to the first bonding structure via a second bonding structure over the carrier substrate.
1. A method for forming a semiconductor structure, comprising:
forming a contact feature over an insulating layer;
forming a first passivation layer over the contact feature;
etching the first passivation layer to form a trench exposing the contact feature;
forming an oxide layer over the contact feature and the first passivation layer and in the trench;
forming a first non-conductive structure over the oxide layer;
patterning the first non-conductive structure to form a gap;
filling a conductive material in the gap to form a first conductive feature, wherein the first non-conductive structure and the first conductive feature form a first bonding structure; and
attaching a carrier substrate to the first bonding structure via a second bonding structure over the carrier substrate.
2. The method as claimed in claim 1 , wherein the first conductive feature and the contact feature are electrically isolated.
3. The method as claimed in claim 1 , further comprising performing an annealing process on the first passivation layer before the oxide layer is formed.
4. The method as claimed in claim 1 , wherein a part of a profile of the oxide layer is trapezoidal.
5. The method as claimed in claim 1 , further comprising:
forming a second passivation layer over the contact feature before forming the first passivation layer, wherein a shape of the second passivation layer corresponds to a shape of the contact feature.
6. The method as claimed in claim 5 , wherein a thickness of the first passivation layer is greater than a thickness of the second passivation layer.
7. The method as claimed in claim 5 , further comprising forming a third passivation layer over the first passivation layer before forming the oxide layer, wherein the first passivation layer and the third passivation layer comprise different materials.
8. The method as claimed in claim 1 , wherein attaching the carrier substrate to the first bonding structure via the second bonding structure over the carrier substrate is conducted at a temperature in a range from about 300° C. to about 600° C.
9. The method as claimed in claim 1 , wherein the first non-conductive structure is a tri-layer structure.
10. A method for forming a semiconductor structure, comprising:
forming a contact feature over an insulating layer;
forming a first passivation layer over the contact feature, wherein the first passivation layer has a first portion over the contact feature and a second portion over the insulating layer, and a top surface of the first portion is higher than a top surface of the second portion;
patterning the first portion of the first passivation layer to form a trench exposing the contact feature;
forming an oxide layer covering both the first portion and the second portion of the first passivation layer and extending into the trench; and
forming a first bonding structure over the oxide layer,
wherein the first bonding structure comprises a first conductive feature embedded in a first non-conductive structure.
11. The method as claimed in claim 10 , wherein forming the first bonding structure over the oxide layer comprises:
depositing a tri-layer structure over the oxide layer to form the first non-conductive structure;
patterning the first non-conductive structure to form a gap;
depositing a conductive material over the first non-conductive structure and the oxide layer and in the gap; and
planarizing the conductive material until a top surface of the first non-conductive structure is exposed, forming the first conductive feature in the gap.
12. The method as claimed in claim 11 , further comprising:
depositing a bottom structure over a carrier substrate;
depositing a second non-conductive structure over the bottom structure;
patterning the second non-conductive structure to form an opening, wherein the bottom structure is exposed by the opening; and
filling the conductive material in the opening to form a second conductive feature, wherein the second non-conductive structure and the second conductive feature form a second bonding structure; and
attaching the carrier substrate to the first bonding structure via the second bonding structure over the carrier substrate.
13. The method as claimed in claim 12 , wherein a number of layers of the bottom structure is identical to a number of layers of the second non-conductive structure.
14. The method as claimed in claim 12 , wherein the first conductive feature is in direct contact with the second conductive feature.
15. The method as claimed in claim 12 , wherein the first conductive feature is aligned with the second conductive feature.
16. The method as claimed in claim 12 , wherein filling the conductive material in the opening comprises:
depositing the conductive material over the second non-conductive structure and in the opening; and
planarizing the conductive material until the conductive material is substantially level with the second non-conductive structure.
17. A method for forming a semiconductor structure, comprising:
forming a first semiconductor wafer, comprising:
forming a contact feature over an insulating layer;
forming a first passivation layer over the contact feature, wherein the first passivation layer has a first portion and a second portion, and a tapered sidewall connects a first top surface of the first portion and a second top surface of the second portion;
forming an oxide layer covering both the first portion and the second portion of the first passivation layer, wherein the oxide layer comprises an extending portion extending through the first portion of the first passivation layer; and
forming a first bonding structure over the oxide layer; and
attaching the first semiconductor wafer to a first carrier substrate via the first bonding structure and a second bonding structure over the first carrier substrate.
18. The method as claimed in claim 17 , further comprising planarizing the first passivation layer before forming the oxide layer, wherein planarizing the first passivation layer comprises partially removing the first portion of the first passivation layer without removing the second portion of the first passivation layer.
19. The method as claimed in claim 17 , further comprising:
attaching a second semiconductor wafer to a second carrier substrate via a third bonding structure;
bonding the first semiconductor wafer to the second semiconductor wafer via a fourth bonding structure;
wherein a TSV in the first semiconductor wafer is electrically connected to a metallization structure in the second semiconductor wafer,
wherein the first semiconductor wafer and the first carrier substrate are electrically isolated, the second semiconductor wafer and the second carrier substrate are electrically isolated, and the first semiconductor wafer and the second semiconductor wafer are electrically connected,
wherein the first bonding structure, the second bonding structure, the third bonding structure, and the fourth bonding structure all comprise a conductive feature embedded in a non-conductive structure.
20. The method as claimed in claim 17 , further comprising:
polishing the first carrier substrate, the second bonding structure, and the first bonding structure until the first passivation layer of the first semiconductor wafer is exposed;
forming a post passivation layer over the first passivation layer;
etching the post passivation layer to form a post trench exposing the contact feature;
forming a polymeric layer over the post passivation layer and on a sidewall of the post trench; and
forming a conducive bump in the post trench.