IP Library Granted Patent US 11,081,556
Granted Patent B2
US 11,081,556 · App. 16/781,049 · Granted Aug 3, 2021

Silicon carbide semiconductor device

Inventor: Hiroyuki Kamada (Osaka, JP)
Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
H01L29/41741H01L29/1608H01L29/7813
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Quick Facts
Patent No.
US 11,081,556
App. No.
16/781,049
Granted
Aug 3, 2021
Kind
B2
Abstract

A silicon carbide semiconductor device includes a silicon carbide substrate, a gate insulating layer provided on a surface of the silicon carbide substrate, a gate electrode provided on the gate insulating layer, a first insulting layer provided on the gate electrode, a first layer provided on the first insulating layer, a second insulating layer provided on the first insulating layer, and an interconnect layer provided on the second insulating layer. The second insulating layer includes SiN or SiON. The first layer includes one of Ti, TiN, Ta, and TaN. The interconnect layer includes Al or Cu.

Claims (101)

1. A silicon carbide semiconductor device comprising:

a silicon carbide substrate;

a gate insulating layer provided on a first surface of the silicon carbide substrate;

a gate electrode provided on the gate insulating layer;

a first insulting layer provided on the gate electrode;

a first layer provided on the first insulating layer;

a second layer provided on the first layer;

a third layer provided on the second layer;

a second insulating layer provided on the first insulating layer; and

an interconnect layer provided on the second insulating layer,

wherein the second insulating layer is provided on the third layer,

wherein the second insulating layer includes SiN or SiON,

wherein the first layer includes one of Ti, TiN, Ta, and TaN,

wherein the second layer includes Ni or TiAlSi,

wherein the third layer includes one of Ti, TiN, Ta, and TaN, and

wherein the interconnect layer includes Al or Cu.

2. The silicon carbide semiconductor device as claimed in claim 1 , wherein

the first layer has a thickness of 33 nm or greater and 120 nm or less, and

the third layer has a thickness of 5 nm or greater and 30 nm or less.

3. The silicon carbide semiconductor device as claimed in claim 2 , wherein

the first layer includes one of Ti, TiN, and a laminated layer of Ti and TiN,

wherein the second layer includes Ni, and

the third layer includes one of Ti, TiN, and a laminated layer of Ti and TiN.

4. The silicon carbide semiconductor device as claimed in claim 2 , further comprising:

a source electrode, including an alloy layer of Ni and Si, and provided on the first surface of the silicon carbide substrate.

5. The silicon carbide semiconductor device as claimed in claim 2 , further comprising:

a gate trench provided on the first surface of the silicon carbide substrate,

wherein the gate insulating layer is provided on an inner wall of the gate trench, and

wherein the gate electrode is provided on the gate insulating layer at the gate trench.

6. The silicon carbide semiconductor device as claimed in claim 1 , wherein

the first layer includes one of Ti, TiN, and a laminated layer of Ti and TiN,

wherein the second layer includes Ni, and

the third layer includes one of Ti, TiN, and a laminated layer of Ti and TiN.

7. The silicon carbide semiconductor device as claimed in claim 6 , further comprising:

a source electrode, including an alloy layer of Ni and Si, and provided on the first surface of the silicon carbide substrate.

8. The silicon carbide semiconductor device as claimed in claim 6 , further comprising:

a gate trench provided on the first surface of the silicon carbide substrate,

wherein the gate insulating layer is provided on an inner wall of the gate trench, and

wherein the gate electrode is provided on the gate insulating layer at the gate trench.

9. The silicon carbide semiconductor device as claimed in claim 1 , further comprising:

a source electrode, including an alloy layer of Ni and Si, and provided on the first surface of the silicon carbide substrate.

10. The silicon carbide semiconductor device as claimed in claim 1 , further comprising:

a gate trench provided on the first surface of the silicon carbide substrate,

wherein the gate insulating layer is provided on an inner wall of the gate trench, and

wherein the gate electrode is provided on the gate insulating layer at the gate trench.

11. The silicon carbide semiconductor device as claimed in claim 1 , further comprising;

a drain electrode provided on a second surface of the silicon carbide substrate, opposite to the first surface provided with the gate electrode.

12. A silicon carbide semiconductor device comprising:

a silicon carbide substrate;

a gate insulating layer provided on a first surface of the silicon carbide substrate;

a gate electrode provided on the gate insulating layer;

a first insulting layer provided on the gate electrode;

a first layer provided on the first insulating layer;

a second layer provided on the first layer;

a second insulating layer provided on the first insulating layer; and

an interconnect layer provided on the second insulating layer,

wherein the second insulating layer is provided on the second layer,

wherein the first layer includes one of Ti, TiN, Ta, and TaN,

wherein the second layer includes one of Ti, TiN, Ta, and TaN,

wherein the second insulating layer includes SiN or SiON, and

wherein the interconnect layer includes Al or Cu.

13. The silicon carbide semiconductor device as claimed in claim 12 , further comprising:

a source electrode, including an alloy layer of Ni and Si, and provided on the first surface of the silicon carbide substrate.

14. The silicon carbide semiconductor device as claimed in claim 12 , further comprising:

a gate trench provided on the first surface of the silicon carbide substrate,

wherein the gate insulating layer is provided on an inner wall of the gate trench, and

wherein the gate electrode is provided on the gate insulating layer at the gate trench.

15. A silicon carbide semiconductor device comprising:

a silicon carbide substrate;

a gate insulating layer provided on a first surface of the silicon carbide substrate;

a gate trench provided on the first surface of the silicon carbide substrate;

a gate electrode provided on the gate insulating layer;

a first insulting layer provided on the gate electrode;

a first layer provided on the first insulating layer;

a second insulating layer provided on the first insulating layer; and

an interconnect layer provided on the second insulating layer,

wherein the gate insulating layer is provided on an inner wall of the gate trench,

wherein the gate electrode is provided on the gate insulating layer at the gate trench,

wherein the first layer includes one of Ti, TiN, Ta, and TaN,

wherein the second insulating layer includes SiN or SiON, and

wherein the interconnect layer includes Al or Cu.

16. The silicon carbide semiconductor device as claimed in claim 15 , further comprising;

a drain electrode provided on a second surface of the silicon carbide substrate, opposite to the first surface provided with the gate electrode.

17. A silicon carbide semiconductor device comprising:

a silicon carbide substrate;

a gate insulating layer provided on a first surface of the silicon carbide substrate;

a gate electrode provided on the gate insulating layer;

a first insulting layer provided on the gate electrode;

a first layer provided on the first insulating layer;

a second insulating layer provided on the first insulating layer;

an interconnect layer provided on the second insulating laver; and

a drain electrode provided on a second surface of the silicon carbide substrate, opposite to the first surface provided with the gate electrode,

wherein the first layer includes one of Ti, TiN, Ta, and TaN,

wherein the second insulating layer includes SiN or SiON, and

wherein the interconnect layer includes Al or Cu.

18. The silicon carbide semiconductor device as claimed in claim 17 , further comprising:

a source electrode, including an alloy layer of Ni and Si, and provided on the first surface of the silicon carbide substrate.

19. The silicon carbide semiconductor device as claimed in claim 18 , further comprising:

a gate trench provided on the first surface of the silicon carbide substrate,

wherein the gate insulating layer is provided on an inner wall of the gate trench, and

wherein the gate electrode is provided on the gate insulating layer at the gate trench.

Assignments (3)
NUNC PRO TUNC ASSIGNMENT Recorded Jul 1, 2026
From: SUMITOMO ELECTRIC INDUSTRIES, LTD.
To: MITSUMI ELECTRIC CO., LTD.
Reel/Frame 075871/0320 →
CORRECTIVE ASSIGNMENT TO CORRECT THE CONVEYING PARTY DATA PREVIOUSLY RECORDED AT REEL: 051708 FRAME: 0566. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Feb 10, 2020
From: KAMADA, HIROYUKI
To: SUMITOMO ELECTRIC INDUSTRIES, LTD.
Reel/Frame 051867/0662 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2020
From: KAMADA, HIROYUK
To: SUMITOMO ELECTRIC INDUSTRIES, LTD.
Reel/Frame 051708/0566 →
Priority Claims (1)
JP JP2019-019800 · Feb 6, 2019 · national
Continuity (1)
Related Publication 20200251564A1 · Aug 6, 2020