Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device comprises a cell array including a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells arranged in matrix and connected at intersections of the first and second lines between both lines, each memory cell containing a serial circuit of an electrically erasable programmable variable resistive element of which resistance is nonvolatilely stored as data and a non-ohmic element; and a plurality of access circuits operative to simultaneously access the memory cells physically separated from each other in the cell array.
1. A nonvolatile semiconductor memory device, comprising:
a first memory cell array including a first line extending in a first direction, a second line extending in a second direction intersecting the first direction, and a first memory cell arranged at an intersection of the first line and the second line, the first memory cell including a first variable resistive element, the first variable resistive element arranged between the first line and the second line;
a second memory cell array including a third line extending in the first direction, a fourth line extending in the second direction, and a second memory cell arranged at an intersection of the third line and the fourth line, the second memory cell including a second variable resistive element, the second variable resistive element arranged between the third line and the fourth line, and the second memory cell array being directly adjacent to the first memory cell array in the first direction;
a first column control circuit connected, between the first memory cell array and the second memory cell array in the first direction, to the first line of the first memory cell array and configured to operate the first line;
a second column control circuit connected to the third line of the second memory cell array, apart from the first column control circuit in the first direction and configured to operate the third line; and
a first row control circuit configured to operate the second line; and
a second row control circuit configured to operate the fourth line;
wherein the first column control circuit is formed below the first memory cell array in a third direction perpendicular to the first and the second directions, and the second column control circuit is formed below the second memory cell array in the third direction, and wherein
the nonvolatile semiconductor memory device further comprises an interconnection provided between the second memory cell array and the second column control circuit in the third direction.
2. The nonvolatile semiconductor memory device according to claim 1 , wherein each of the first and second variable resistive elements includes a chalcogenide compound.
3. The nonvolatile semiconductor memory device according to claim 1 , wherein each of the first and second memory cells includes a non-ohmic element.
4. The nonvolatile semiconductor memory device according to claim 1 , wherein each of the first and second column control circuits includes a plurality of sense amplifier circuits configured to sense/amplify data on a memory cell array basis.
5. The nonvolatile semiconductor memory device according to claim 1 , wherein the first row control circuit is arranged apart from the first memory cell array in the second direction and the second row control circuit is arranged apart from the second memory cell array in the second direction.
6. The nonvolatile semiconductor memory device according to claim 1 , wherein the first column control circuit and the second column control circuit are provided in a same layer.
7. A nonvolatile semiconductor memory device, comprising:
a first memory cell array including a first line extending in a first direction, a second line extending in a second direction intersecting the first direction, and a first memory cell arranged at an intersection of the first line and the second line, the first memory cell including a first variable resistive element, the first variable resistive element arranged between the first line and the second line;
a second memory cell array including a third line extending in the first direction, a fourth line extending in the second direction, and a second memory cell arranged at an intersection of the third line and the fourth line, the second memory cell including a second variable resistive element, the second variable resistive element arranged between the third line and the fourth line, and the second memory cell array being directly adjacent to the first memory cell array in the first direction;
a first column control circuit being provided below the first memory cell array in a third direction perpendicular to the first and second directions, and connected to the first line of the first memory cell array and configured to operate the first line;
a second column control circuit being provided below the second memory cell array in the third direction, connected to the third line of the second memory cell array and configured to operate the third line; and
a first row control circuit configured to operate the second line; and
a second row control circuit configured to operate the fourth line;
wherein the first column control circuit is formed below the first memory cell array in the third direction, and the second column control circuit is formed below the second memory cell array in the third direction, and wherein
the nonvolatile semiconductor memory device further comprises an interconnection provided between the first memory cell array and the first column control circuit in the third directiOn.
8. The nonvolatile semiconductor memory device according to claim 7 , wherein each of the first and second variable resistive elements includes a chalcogenide compound.
9. The nonvolatile semiconductor memory device according to claim 7 , wherein each of the first and second memory cells includes a non-ohmic element.
10. The nonvolatile semiconductor memory device according to claim 7 , wherein each of the first and second column control circuits includes a plurality of sense amplifier circuits configured to sense/amplify data on a memory cell array basis.
11. The nonvolatile semiconductor memory device according to claim 7 , wherein the first row control circuit is arranged apart from the first memory cell array in the second direction and the second row control circuit is arranged apart from the second memory cell array in the second direction.
12. The nonvolatile semiconductor memory device according to claim 7 , wherein the first column control circuit and the second column control circuit are provided in a same layer.
13. A nonvolatile semiconductor memory device, comprising:
a substrate;
a first memory cell array being provided above the substrate, including a first line extending in a first direction, a second line extending in a second direction intersecting the first direction, and a first memory cell arranged at an intersection of the first line and the second line, the first memory cell including a first variable resistive element arranged between the first line and the second line;
a second memory cell array being provided above the substrate, including a third line extending in the first direction, a fourth line extending in the second direction, and a second memory cell arranged at an intersection of the third line and the fourth line, the second memory cell including a second variable resistive element arranged between the third line and the fourth line, and the second memory cell array being directly adjacent to the first memory cell array in the first direction;
a first column control circuit formed below the first memory cell array, the first column control circuit, connected, between the first memory cell array and the second memory cell array in the first direction, to the first line of the first memory cell array and configured to operate the first line;
a second column control circuit is formed below the second memory cell array, the second column control circuit; connected to the third line of the second memory cell array, provided apart from the first column control circuit in the first direction and configured to operate the third line; and
a first row control circuit configured to operate the second line; and
a second row control circuit configured to operate the fourth line, wherein
the nonvolatile semiconductor memory device further comprises an interconnection provided between the second memory cell array and the second column control circuit in the third direction.
14. The nonvolatile semiconductor memory device according to claim 13 , wherein each of the first and second variable resistive elements includes a chalcogenide compound.
15. The nonvolatile semiconductor memory device according to claim 13 , wherein each of the first and second memory cells includes a non-ohmic element.
16. The nonvolatile semiconductor memory device according to claim 13 , wherein the first row control circuit is arranged apart from the first memory cell array in the second direction and the second row control circuit is arranged apart from the second memory cell array in the second direction.
17. The nonvolatile semiconductor memory device according to claim 13 , wherein the first column control circuit and the second column control circuit are provided in a same layer.