Method of manufacturing a semiconductor device and a semiconductor device
A semiconductor device includes a channel region, a source/drain region adjacent to the channel region, and a source/drain epitaxial layer. The source/drain epitaxial layer includes a first epitaxial layer epitaxially formed on the source/drain region, a second epitaxial layer epitaxially formed on the first epitaxial layer and a third epitaxial layer epitaxially formed on the second epitaxial layer. The first epitaxial layer includes at least one selected from the group consisting of a SiAs layer, a SiC layer and a SiCP layer.
1. A semiconductor device, comprising:
a semiconductor wire having a channel region;
a gate structure wrapping around the channel region;
a source/drain region adjacent to the channel region; and
a source/drain epitaxial layer, wherein:
the source/drain epitaxial layer includes a first epitaxial layer epitaxially formed on the source/drain region, a second epitaxial layer epitaxially formed on the first epitaxial layer and a third epitaxial layer epitaxially formed on the second epitaxial layer, and
the first epitaxial layer includes a SiC layer or a SiCAs layer.
2. The semiconductor device of claim 1 , wherein the second epitaxial layer includes a SiP layer.
3. The semiconductor device of claim 2 , wherein the third epitaxial layer includes at least one selected from the group consisting of a SiAs layer, a SiC layer, a SiCAs layer and a SiCP layer.
4. The semiconductor device of claim 3 , wherein the third epitaxial layer includes one of a SiAs layer, a SiC layer and a SiCAs layer.
5. The semiconductor device of claim 3 , wherein the third epitaxial layer includes a SiP layer having a lower P concentration than the second epitaxial layer.
6. The semiconductor device of claim 1 , wherein the second epitaxial layer has a greater thickness than the first epitaxial layer and the third epitaxial layer.
7. The semiconductor device of claim 6 , wherein a thickness of the first epitaxial layer is in a range from 1 nm to 3 nm.
8. The semiconductor device of claim 6 , wherein a thickness of the third epitaxial layer is in a range from 1 nm to 3 nm.
9. The semiconductor device of claim 1 , wherein:
the first epitaxial layer includes a SiCAs layer, and
a concentration of As in the first epitaxial layer is in a range from 1×10 20 atoms/cm 3 to 5×10 21 atoms/cm 3 .
10. The semiconductor device of claim 1 , wherein:
the second epitaxial layer includes a SiP layer, and
a concentration of P in the SiP layer is in a range from 1×10 20 atoms/cm 3 to 5×10 21 atoms/cm 3 .
11. The semiconductor device of claim 1 , wherein:
the third epitaxial layer includes a SiAs layer or a SiCAs layer, and
a concentration of As in the third epitaxial layer is in a range from 1×10 20 atoms/cm 3 to 5×10 21 atoms/cm 3 .
12. The semiconductor device of claim 1 , wherein:
a plurality of semiconductor wires vertically arranged over a bottom fin structure, and
each of the plurality of semiconductor wires has the channel region and the source/drain region.
13. The semiconductor device of claim 12 , wherein the first epitaxial layer wraps around the source/drain region of each of the plurality of semiconductor wires, and the first epitaxial layer wrapping around one source/drain region is separated from the first epitaxial layer wrapping around an adjacent one source/drain region.
14. The semiconductor device of claim 13 , wherein the second epitaxial layer wraps around the source/drain region covered with the first epitaxial layer, and fills gaps between adjacent source/drain regions.
15. The semiconductor device of claim 14 , wherein the third epitaxial layer covers an outer surface of the second epitaxial layer and is separated from the first epitaxial layer.
16. The semiconductor device of claim 1 , wherein a concentration of As in the first epitaxial layer is in a range from 1×10 20 atoms/cm 3 to 5×10 21 atoms/cm 3 .
17. A semiconductor device including a gate-all-around field effect transistor (GAA FET), the GAA FET comprising:
a plurality of semiconductor wires each having a channel region and a source/drain region adjacent to the channel region; and
a source/drain epitaxial layer, wherein:
the source/drain epitaxial layer includes a first epitaxial layer epitaxially wrapping around the source/drain region of each of the semiconductor wires, a second epitaxial layer epitaxially formed on the first epitaxial layer and a third epitaxial layer epitaxially formed on the second epitaxial layer,
the second epitaxial layer includes P,
the first epitaxial layer includes a SiC layer or a SiCAs layer, and
the third epitaxial layer includes a SiAs layer, a SiC layer or a SiCAs layer.
18. The semiconductor device of claim 17 , wherein the third epitaxial layer includes a material different from the first epitaxial layer.
19. The semiconductor device of claim 18 , wherein:
the first epitaxial layer and the third epitaxial layer contain As, and
a concentration of As in the first epitaxial layer is smaller than a concentration of As in the third epitaxial layer.
20. A semiconductor device including a gate-all-around field effect transistor (GAA FET), the GAA FET comprising:
a plurality of semiconductor nanowires each having a channel region and a source/drain region adjacent to the channel region; and
a source/drain epitaxial layer,
wherein: the source/drain epitaxial layer includes a first epitaxial layer epitaxially wrapping around on the source/drain region of each of the semiconductor nanowires, a second epitaxial layer epitaxially formed on the first epitaxial layer and a third epitaxial layer epitaxially formed on the second epitaxial layer,
the first epitaxial layer includes C, and the third epitaxial layer includes at least one element of As or C, and
the second epitaxial layer includes a SiAs layer, a SiC layer or a SiCAs layer.