Preserving underlying dielectric layer during MRAM device formation

1. A method of forming a magnetic random access memory (MRAM) device, the method comprising the steps of:

depositing a first dielectric cap layer onto a substrate over a logic area and a memory area of the substrate;

depositing a sacrificial metal layer onto the first dielectric cap layer;

patterning the sacrificial metal layer, wherein the patterned sacrificial metal layer is present over the first dielectric cap layer in at least the logic area of the substrate;

depositing a second dielectric cap layer onto the first dielectric cap layer over the patterned sacrificial metal layer;

forming an MRAM stack on the second dielectric cap layer;

patterning the MRAM stack using ion beam etching into at least one memory cell in the memory area of the substrate, wherein the patterned sacrificial metal layer protects the first dielectric cap layer in the logic area of the substrate during the patterning of the MRAM stack; and

removing the patterned sacrificial metal layer.

2. The method of claim 1 , wherein the substrate comprises interconnects formed therein in both the logic area and the memory area.

3. The method of claim 1 , wherein the first dielectric cap layer and the second dielectric cap layer each comprises a material selected from the group consisting of: silicon carbide (SiC), silicon nitride (SiN), silicon carbon nitride (SiCN), hydrogen containing silicon carbon nitride (SiCNH), and combinations thereof.

4. The method of claim 1 , wherein the sacrificial metal layer comprises a material selected from the group consisting of: tantalum nitride (TaN), titanium nitride (TiN), and combinations thereof.

5. The method of claim 1 , wherein the patterned sacrificial metal layer is also present over the first dielectric cap layer in the memory area of the substrate.

6. The method of claim 5 , wherein the patterned sacrificial metal layer protects the first dielectric cap layer in the memory area of the substrate during the patterning of the MRAM stack.

7. The method of claim 1 , further comprising the step of:

forming interconnects in the first dielectric cap layer and the second dielectric cap layer in the memory area of the substrate.

8. The method of claim 1 , wherein the MRAM stack comprises:

a bottom electrode layer disposed on the second dielectric cap layer;

a magnetic tunnel junction (MTJ) layer disposed on the bottom electrode layer; and

a top electrode layer disposed on the MTJ layer.

9. The method of claim 8 , wherein, following the patterning of the MRAM stack, the bottom electrode layer forms a bottom electrode of the at least one memory cell, the MTJ layer forms am MTJ of the at least one memory cell, and the top electrode layer forms a top electrode of the at least one memory cell.

10. The method of claim 9 , further comprising the steps of:

depositing an interlayer dielectric (ILD) over the substrate and surrounding the at least one memory cell; and

forming interconnects in the ILD in contact with the top electrode of the at least one memory cell.

11. The method of claim 1 , further comprising the step of:

forming spacers along sidewalls of the at least one memory cell prior to removing the patterned sacrificial metal layer.

12. The method of claim 11 , wherein the spacers comprise a material selected from the group consisting of: SiN, SiCN, SiCNH and combinations thereof.

13. A method of forming an MRAM device, the method comprising the steps of:

depositing a first dielectric cap layer onto a substrate over a logic area and a memory area of the substrate;

depositing a sacrificial metal layer onto the first dielectric cap layer;

patterning the sacrificial metal layer, wherein the patterned sacrificial metal layer is present over the first dielectric cap layer the logic area and in the memory area of the substrate;

depositing a second dielectric cap layer onto the first dielectric cap layer over the patterned sacrificial metal layer;

forming an MRAM stack on the second dielectric cap layer;

patterning the MRAM stack using ion beam etching into at least one memory cell in the memory area of the substrate, wherein the patterned sacrificial metal layer protects the first dielectric cap layer in the logic area and in the memory area of the substrate during the patterning of the MRAM stack;

forming spacers along sidewalls of the at least one memory cell prior to removing the patterned sacrificial metal layer; and

removing the patterned sacrificial metal layer.

14. The method of claim 13 , wherein the sacrificial metal layer comprises a material selected from the group consisting of: TaN, TiN, and combinations thereof.

15. The method of claim 13 , wherein the substrate comprises first interconnects formed therein in both the logic area and the memory area, the method further comprising the steps of:

forming second interconnects in the first dielectric cap layer and the second dielectric cap layer in contact with the first interconnects in the memory area of the substrate;

depositing an ILD over the substrate and surrounding the at least one memory cell; and

forming third interconnects in the ILD in contact with the top electrode of the at least one memory cell.

16. The method of claim 13 , wherein the MRAM stack comprises:

a bottom electrode layer disposed on the second dielectric cap layer;

an MTJ layer disposed on the bottom electrode layer; and

a top electrode layer disposed on the MTJ layer.

17. The method of claim 16 , wherein, following the patterning of the MRAM stack, the bottom electrode layer forms a bottom electrode of the at least one memory cell, the MTJ layer forms an MTJ of the at least one memory cell, and the top electrode layer forms a top electrode of the at least one memory cell.