Granted Patent B2

US 12,389,803 · App. 17/534,485 · Granted Aug 12, 2025

Inventors: Ashim Dutta (Clifton Park, NY); Shyng-Tsong Chen (Rensselaer, NY); Terry A. Spooner (Mechanicville, NY); Chih-Chao Yang (Glenmont, NY)

Assignee: International Business Machines Corporation

H10N50/01G11C11/161H01L21/76885H01L23/5226H10B61/00H10N50/10H10N50/80

Abstract

Claims (52)

1. A method comprising:

providing a substrate having an embedded memory area interconnect structure and an embedded non-memory area interconnect structure, the memory area interconnect structure comprising metal interconnects formed in dielectric material;

forming a dielectric cap layer on exposed surfaces of the memory area and the non-memory area;

forming a bottom metal contact on a first metal interconnect of the memory area interconnect structure, the bottom metal contact in a trench in the dielectric cap layer;

forming a memory element stack pillar on the bottom metal contact;

forming a dielectric layer on exposed surfaces of the memory area and the non-memory area utilizing a non-conformal deposition process; and

removing the dielectric layer from sidewalls of the memory element stack pillar, exposing sidewalls of a magnetic tunnel junction (MTJ) stack of the memory element pillar.

2. The method of claim 1 , wherein forming the memory element stack pillar on the bottom metal contact comprises:

forming memory element stack layers on exposed surfaces of the memory area and the non-memory area; and

selectively removing portions of the memory element stack layers to form the memory element stack pillar on the bottom metal contact.

3. The method of claim 1 , wherein:

subsequent to forming the memory element stack pillar, redeposited material is present on the sidewalls of the memory element stack pillar; and

removing the dielectric layer from the sidewalls of the memory element stack pillar further comprises removing the redeposited material from the sidewalls of the memory element stack pillar.

4. The method of claim 1 , wherein the non-conformal deposition process comprises a physical vapor deposition process.

5. The method of claim 2 , wherein selectively removing portions of the memory element stack layers comprises an ion beam etching process.

6. The method of claim 1 , wherein forming the bottom metal contact in the trench comprises:

forming the trench, the trench formed over the first metal interconnect of the memory area interconnect structure; and

forming the bottom metal contact in the trench.

7. The method of claim 1 , further comprising:

forming a first top contact over the memory element stack pillar; and

forming a second top contact over the metal interconnect of the non-memory area interconnect structure.

8. The method of claim 1 , further comprising:

subsequent to removing the dielectric layer from the sidewalls of the memory element stack pillar, forming a pillar encapsulation layer on exposed surfaces of the memory area and the non-memory area.

9. The method of claim 8 , further comprising:

performing an anisotropic etch process to expose the dielectric layer; and

forming an interlayer dielectric layer on exposed surfaces of the memory area and the non-memory area.

10. The method of claim 8 , further comprising:

performing an anisotropic etch process that removes a portion of the pillar encapsulation layer; and

forming an interlayer dielectric layer on exposed surfaces of the memory area and the non-memory area.

11. A semiconductor structure comprising:

an embedded memory area interconnect structure and an embedded non-memory area interconnect structure, the memory area interconnect structure comprising metal interconnects formed in dielectric material;

a dielectric cap layer in the memory area and the non-memory area;

a bottom metal contact on a metal interconnect of the memory area interconnect structure, the bottom metal contact in a trench formed in the dielectric cap layer;

a dielectric layer on the dielectric cap layer, wherein the dielectric cap layer and the dielectric layer have a combined thickness of greater than fifty nanometers; and

a memory element stack pillar on the bottom metal contact.

12. The semiconductor structure of claim 11 , wherein the memory element stack pillar comprises a magnetic tunnel junction (MTJ) stack.

13. The semiconductor structure of claim 11 , further comprising:

a barrier layer present on the metal interconnects formed in the dielectric material and the bottom metal contact.

14. The semiconductor structure of claim 11 , further comprising:

a top contact on a metal interconnect structure of the non-memory area interconnect structure.

15. The semiconductor structure of claim 11 , further comprising:

a top contact over the memory element stack pillar.

16. The semiconductor structure of claim 11 , further comprising:

a pillar encapsulation layer on sidewalls of the memory element stack pillar, the pillar encapsulation layer comprising dielectric material.

17. The semiconductor structure of claim 15 , further comprising:

an interlayer dielectric layer on exposed surfaces of a pillar encapsulation layer, the dielectric cap, and sidewalls of the top contact.

18. The semiconductor structure of claim 11 , further comprising:

a pillar encapsulation layer on the dielectric layer and sidewalls of the memory element stack pillar, the pillar encapsulation layer comprising dielectric material.

19. The semiconductor structure of claim 12 , further comprising:

a top electrode on the MTJ stack; and

a bottom electrode between the MTJ stack and the bottom metal contact.

20. The method of claim 1 , wherein subsequent to removing the dielectric layer from the sidewalls of the memory element stack pillar, a portion of the dielectric layer remains that completely covers top surfaces of the dielectric cap layer.

Assignments (1)

Continuity (1)

References Cited (46)