Semiconductor device and semiconductor package

1. A semiconductor device, comprising:

a semiconductor substrate;

at least one semiconductor structure;

an interlayer insulating layer disposed on the semiconductor substrate and the semiconductor structure;

at least one first via structure penetrating the semiconductor substrate and the interlayer insulating layer, the first via structure including a first region having a first width at an upper surface of the interlayer insulating layer and a second region extending from the first region and having a second width at a lower surface of the semiconductor substrate, wherein a side surface of the first region and a side surface of the second region have different profiles at a boundary between the first region and the second region; and

at least one second via structure penetrating the semiconductor substrate and the interlayer insulating layer and having a third width greater than the first width at the upper surface of the interlayer insulating layer.

2. The semiconductor device of claim 1 , wherein the first width is less than the second width.

3. The semiconductor device of claim 1 , wherein at least a portion of the second region has a width increasing from the boundary.

4. The semiconductor device of claim 1 , wherein at least a portion of the first region has a width increasing from the boundary.

5. The semiconductor device of claim 1 , wherein the side surface of the second region has a curved shape in a region adjacent to the boundary.

6. The semiconductor device of claim 5 , wherein the side surface of the second region has embossed structures.

7. The semiconductor device of claim 1 , wherein the at least one first via structure and the at least one second via structure are configured to transfer different signals.

8. The semiconductor device of claim 7 , wherein the at least one first via structure is configured to transfer a data signal, and the at least one second via structure transfers is configured to transfer a power signal.

9. The semiconductor device of claim 1 , wherein a side surface of the at least one first via structure and a side surface of the at least one second via structure have different profiles.

10. The semiconductor device of claim 1 , wherein the boundary is in the semiconductor substrate.

11. The semiconductor device of claim 1 , wherein a length of the at least one first via structure is the same as a length of the at least one second via structure.

12. The semiconductor device of claim 1 , wherein the third width is less than the second width.

13. The semiconductor device of claim 1 , wherein the third width is greater than the second width.

14. A semiconductor package, comprising:

a first semiconductor device; and

a second semiconductor device stacked with the first semiconductor device,

wherein the first semiconductor device includes at least one first via structure and at least one second via structure penetrating the first semiconductor device, and

wherein the at least one first via structure includes a first region and a second region, the first region having a first width on an upper surface of the first semiconductor device, the second region having a second width on a lower surface of the first semiconductor device, and the second width being different from the first width, and

a width of a boundary surface between the first region and the second region is less than the first width.

15. The semiconductor package of claim 14 , wherein the at least one second via structure has a third width greater than the first width.

16. The semiconductor package of claim 14 , wherein the first semiconductor device and the second semiconductor device are mounted on a package substrate, and the first semiconductor device includes at least one memory die configured to store data.

17. The semiconductor package of claim 16 ,

wherein the second semiconductor device includes at least one memory die configured to store data, and

wherein the semiconductor package further comprises a memory controller mounted on the package substrate at a same level as a level of the second semiconductor device and is configured to control the first semiconductor device and the second semiconductor device.

18. The semiconductor package of claim 16 , wherein the second semiconductor device includes a memory controller configured to control the first semiconductor device.

19. The semiconductor package of claim 16 , wherein

the at least one first via structure is in a first area of the first semiconductor device and the at least one first via structure is configured to transfer a data signal, and

the at least one second via structure is in a second area of the first semiconductor device, the second area of the first semiconductor device separated from the first region of the first semiconductor device and the at least one second via structure configured to transfer a power signal.

20. A semiconductor package, comprising:

a package substrate;

a plurality of memory dies mounted on the package substrate, the plurality of memory dies including memory cells configured to store data, and the plurality of memory dies stacked in a direction perpendicular to an upper surface of the package substrate;

a first via structure penetrating the plurality of memory dies and configured to provide a transfer path for a data signal; and

a second via structure penetrating the plurality of memory dies and configured to provide a transfer path for a power signal,

wherein a difference between a width of the first via structure at a lower surface of at least one of the plurality of memory dies and a width of the first via structure at an upper surface of the at least one of the plurality of memory dies is less than a difference between a width of the second via structure at a lower surface of at least one of the plurality of memory dies and a width of the second via structure at an upper surface of the plurality of memory dies, and

wherein the width at the upper surface of the first via structure is less than the width at the upper surface of the second via structure.