CMOS circuit with vertically oriented n-type transistor and method of providing same
Techniques and mechanisms for providing a space efficient complementary metal-oxide-semiconductor (CMOS) circuit. In an embodiment, a p-type transistor of a circuit is to conduct current in a direction parallel to a surface of a semiconductor substrate, wherein an n-type thin film transistor (TFT) of the circuit is to conduct current in a direction which is orthogonal to the surface. A first interconnect is directly coupled to each of the two transistors, wherein the first interconnect, a high mobility channel structure of the n-type TFT, and a source or drain of the p-type transistor are on the same line of direction. A second interconnect comprises a conductive path which extends to respective gates of the p-type transistor and the n-type TFT, wherein the conductive path is limited to a region over a footprint of the p-type transistor. In another embodiment, functionality of a logical inverter is provided with the circuit.
1. An integrated circuit comprising:
a p-type transistor on a substrate, the p-type transistor comprising a first drain, a first source, a first gate, and a first semiconductor body which extends between the first source and the first drain along a first line which is parallel to a surface of the substrate;
an n-type thin film transistor (TFT) comprising a second drain, a second source, a second gate, and a second semiconductor body which extends between the second source and the second drain along a second line which is orthogonal to the surface of the substrate, wherein the second gate surrounds the second semiconductor body, and wherein a carrier mobility of the second semiconductor body is equal to or greater than 100 cm 2 /V·s;
a first interconnect coupled to each of the p-type transistor and the n-type TFT, wherein the first interconnect, one of the first source or the first drain, and one of the second source or the second drain are on the second line; and
a second interconnect comprising a conductive path which extends to each of the first gate and the second gate, wherein the conductive path is limited to a region over a footprint of the p-type transistor.
2. The integrated circuit of claim 1 , wherein one of an inverter or a NAND gate includes the p-type transistor and the n-type TFT.
3. The integrated circuit of claim 1 , further comprising:
a second n-type TFT comprising a third drain, a third source, and a third semiconductor body which extends between the third source and the third drain along the second line; and
a third interconnect structure coupled to each of the n-type TFT and the second n-type TFT, wherein the third interconnect is on the second line.
4. The integrated circuit of claim 3 , further comprising:
a second p-type transistor on the substrate, the second p-type transistor comprising a fourth drain, a fourth source, a fourth gate, and a fourth semiconductor body which extends between the fourth source and the fourth drain along a third line which is parallel to the surface of the substrate; and
a fourth interconnect coupled to each of the third gate and the forth gate.
5. The integrated circuit of claim 4 , wherein the p-type transistor and the second p-type transistor are arranged in a side-by-side configuration.
6. The integrated circuit of claim 1 , wherein the second semiconductor body comprises oxygen and at least one of indium, gallium, zinc, titanium, or tin.
7. The integrated circuit of claim 1 , wherein the p-type transistor comprises a second TFT.
8. A method comprising:
forming on a substrate a p-type transistor comprising a first drain, a first source, a first gate, and a first semiconductor body which extends between the first source and the first drain along a first line which is parallel to a surface of the substrate;
forming an n-type thin film transistor (TFT) comprising a second drain, a second source, a second gate, and a second semiconductor body which extends between the second source and the second drain along a second line which is orthogonal to the surface of the substrate, wherein the second gate surrounds the second semiconductor body, and wherein a carrier mobility of the second semiconductor body is equal to or greater than 100 cm 2 /V·s;
coupling each of the p-type transistor and the n-type TFT to a first interconnect, wherein the first interconnect, one of the first source or the first drain, and one of the second source or the second drain are on the second line; and
forming a second interconnect comprising a conductive path which extends to each of the first gate and the second gate, wherein the conductive path is limited to a region over a footprint of the p-type transistor.
9. The method of claim 8 , wherein one of an inverter or a NAND gate includes the p-type transistor and the n-type TFT.
10. The method of claim 8 , further comprising:
forming a second n-type TFT comprising a third drain, a third source, and a third semiconductor body which extends between the third source and the third drain along the second line; and
coupling a third interconnect structure to each of the n-type TFT and the second n-type TFT, wherein the third interconnect is on the second line.
11. The method of claim 8 , wherein the second semiconductor body comprises oxygen and at least one of indium, gallium, zinc, titanium, or tin.
12. The method of claim 8 , wherein the second semiconductor body comprises an amorphous semiconductor.
13. The method of claim 8 , wherein an average size of any crystallites of the second semiconductor body is in a range of 0.5 nanometers (nm) to 5 nm.
14. A system comprising:
an integrated circuit (IC) comprising:
a p-type transistor on a substrate, the p-type transistor comprising a first drain, a first source, a first gate, and a first semiconductor body which extends between the first source and the first drain along a first line which is parallel to a surface of the substrate;
an n-type thin film transistor (TFT) comprising a second drain, a second source, a second gate, and a second semiconductor body which extends between the second source and the second drain along a second line which is orthogonal to the surface of the substrate, wherein the second gate surrounds the second semiconductor body, and wherein a carrier mobility of the second semiconductor body is equal to or greater than 100 cm 2 /V·s;
a first interconnect coupled to each of the p-type transistor and the n-type TFT, wherein the first interconnect, one of the first source or the first drain, and one of the second source or the second drain are on the second line; and
a second interconnect comprising a conductive path which extends to each of the first gate and the second gate, wherein the conductive path is limited to a region over a footprint of the p-type transistor; and
a display device coupled to the IC, the display device to generate a display based on a signal communicated with the IC.
15. The system of claim 14 , wherein one of an inverter or a NAND gate includes the p-type transistor and the n-type TFT.
16. The system of claim 14 , wherein the other of the first source or the first drain is coupled to receive a supply voltage.
17. The system of claim 16 , wherein the other of the second source or the second drain is coupled to receive a ground voltage.
18. The system of claim 14 , the integrated circuit further comprising:
a second n-type TFT comprising a third drain, a third source, and a third semiconductor body which extends between the third source and the third drain along the second line; and
a third interconnect structure coupled to each of the n-type TFT and the second n-type TFT, wherein the third interconnect is on the second line.
19. The system of claim 18 , the integrated circuit further comprising:
a second p-type transistor on the substrate, the second p-type transistor comprising a fourth drain, a fourth source, a fourth gate, and a fourth semiconductor body which extends between the fourth source and the fourth drain along a third line which is parallel to the surface of the substrate; and
a fourth interconnect coupled to each of the third gate and the forth gate.
20. The system of claim 19 , wherein the p-type transistor and the second p-type transistor are arranged in a side-by-side configuration.
21. The system of claim 14 , wherein the second interconnect is coupled to receive a first signal representing a first logic state, and wherein the first interconnect is coupled to output a second signal representing a second logic state based on the first logic state.
22. The system of claim 14 , wherein the second semiconductor body comprises oxygen and at least one of indium, gallium, zinc, titanium, or tin.