Multi-gate device
A multi-gate semiconductor device having a fin element, a gate structure over the fin element, an epitaxial source/drain feature adjacent the fin element; a dielectric spacer interposing the gate structure and the epitaxial source/drain feature.
1. A multi-gate semiconductor device, comprising:
a first layer having a first composition, the first layer extending from a source/drain region of the first layer to a channel region of the first layer;
a second layer having the first composition, the second layer extending from a source/drain region of the second layer to a channel region of the second layer and spaced above the first layer;
a gate structure interposed between the channel region of the first layer and the channel region of the second layer;
an epitaxial layer having a second composition interposing the source/drain region of the first layer and the source drain region of the second layer; and
a dielectric material disposed between the first layer and the second layer, the dielectric material interposing the gate structure and the epitaxial layer.
2. The multi-gate semiconductor device of claim 1 , wherein the dielectric material is silicon germanium oxide.
3. The multi-gate semiconductor device of claim 1 , wherein the dielectric material is at least one of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, or SiOCN.
4. The multi-gate semiconductor device of claim 1 , wherein a second dielectric material different than the dielectric material is disposed on sidewalls of the gate structure.
5. The multi-gate semiconductor device of claim 1 , wherein a thickness of the dielectric material is between approximately 4 nanometers (nm) and approximately 6 nm.
6. The multi-gate semiconductor device of claim 1 , wherein epitaxial layer directly interfaces a first sidewall of the dielectric material and a gate dielectric material of the gate structure directly interfaces a second sidewall of the dielectric material, the second sidewall opposing the first sidewall.
7. The multi-gate semiconductor device of claim 6 , wherein a distance between the first sidewall and the second sidewall is between approximately 4 nanometers (nm) and approximately 6 nm.
8. The multi-gate semiconductor device of claim 1 , wherein the first composition is silicon.
9. A multi-gate semiconductor device, comprising:
a first silicon layer extending from a source/drain region of the first silicon layer to a channel region of the first silicon layer;
a second silicon layer extending from a source/drain region of the second silicon layer to a channel region of the second silicon layer and spaced above the first silicon layer;
a gate structure interposed between the channel region of the first silicon layer and the channel region of the second silicon layer;
an epitaxial layer having a second composition interposing the source/drain region of the first silicon layer and the source/drain region of the second silicon layer; and
a dielectric material disposed between the first silicon layer and the second silicon layer, the dielectric material interposing the gate structure and the epitaxial layer.
10. The multi-gate semiconductor device of claim 9 , wherein the dielectric material includes silicon germanium oxide.
11. The multi-gate semiconductor device of claim 9 , further comprising:
spacer elements abutting a portion of the gate structure overlying the first silicon layer.
12. The multi-gate semiconductor device of claim 11 , wherein the spacer elements have a different composition than the dielectric material.
13. The multi-gate semiconductor device of claim 11 , wherein the spacer elements comprise at least one of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, or SiOCN.
14. The multi-gate semiconductor device of claim 9 , wherein the epitaxial layer extends from a top surface of the second silicon layer to a bottom surface of the first silicon layer.
15. A multi-gate semiconductor device, comprising:
a first layer having a first composition, the first layer extending from a source/drain region of the first layer to a channel region of the first layer;
a second layer having the first composition, the second layer extending from a source/drain region of the second layer to a channel region of the second layer and spaced above the first layer;
a gate structure interposed between the channel region of the first layer and the channel region of the second layer;
an epitaxial layer having a second composition extending from a bottom surface of the first layer in the source/drain region of the first layer to a top surface of the second layer in the source/drain region of the second layer; and
a dielectric material extending between the first layer and the second layer, the dielectric material interposing the gate structure and the epitaxial layer.
16. The multi-gate semiconductor device of claim 15 ,
wherein the dielectric material extends between the bottom surface of the first layer and the top surface of the second layer.
17. The multi-gate semiconductor device of claim 15 , wherein the epitaxial layer extends to a side surface of the first layer and a side surface of the second layer.
18. The multi-gate semiconductor device of claim 15 , wherein the first layer and the second layer include silicon.
19. The multi-gate semiconductor device of claim 15 , wherein the dielectric material interfaces a gate dielectric layer of the gate structure.
20. The multi-gate semiconductor device of claim 15 , wherein the dielectric material extends from an interface with the gate structure to an interface with the epitaxial layer.