Forward error correction mechanism for peripheral component interconnect-express (PCI-E)
Aspects of the embodiments are directed to systems, methods, and devices that can activate forward error correction (FEC) based on the channel loss of a channel. The channel's loss can be characterized as a high loss channel if the channel loss exceeds a predetermined threshold value. For channels with high loss and for those that operate at high data rates (e.g., data rates commensurate with PCIe Gen 4 or Gen 5), FEC can be activated so that the channels can achieve higher data rates.
1. An apparatus comprising:
a downstream port to transmit data blocks across a link, the downstream port comprising circuitry to:
change a first data rate of 64 gigatransfers per second (GT/s) to a second data rate, the second data rate lower than 64 GT/s;
determine error correcting code (ECC) for the data block;
transmit the data block with the ECC at the second data rate below 64 GT/s; and
transmit a skip ordered set (SKP OS) across the link without ECC.
2. The apparatus of claim 1 , wherein the SKP OS is a first SKP OS, and the protocol stack is to transmit a redundant SKP OS after the first SKP OS.
3. The apparatus of claim 1 , wherein the ECC is determined for the data block without including the SKP OS.
4. The apparatus of claim 1 , wherein the second data rate comprises one of 32, 16, or 8 GT/s.
5. The apparatus of claim 1 , wherein the ECC is transmitted with the data blocks at predetermined intervals.
6. The apparatus of claim 1 , wherein the circuitry is to:
determine the second data rate;
causing the link to enter into a recovery state;
changing to the data rate; and
transmit data blocks at the data rate.
7. A method comprising:
determining that a data rate for transmitting data blocks across a link is to change from 64 gigatransfers per second (GT/s) to a data rate below 64 GT/s;
activating forward error correction for the data blocks;
transmitting the data blocks with forward error correction at the data rate below 64 GT/s; and
transmitting skip ordered set (SKP OS) after the data blocks without forward error correction.
8. The method of claim 7 , further comprising determining error correcting code (ECC) for the forward error correction for the data rate below 64 GT/s.
9. The method of claim 8 , further comprising transmitting a portion of the ECC for the data blocks on each lane of a link.
10. The method of claim 7 , further comprising changing the data rate from 64 GT/s to one of 32, 16, or 8 GT/s.
11. The method of claim 7 , further comprising transmitting a first set of SKP OS and transmitting a second, redundant set of SKP OS without forward error correction.
12. The method of claim 7 , further comprising:
determining the data rate for a link to operate that is lower than 64 GT/s;
causing the link to enter into a recovery state; and
changing the data rate to a lower data rate.
13. A system comprising:
a host device comprising:
a downstream port comprising circuitry to transmit data blocks across a link, the downstream port comprising circuitry to:
determine that a first data rate for transmitting data blocks across a link is to change from 64 gigatransfers per second (GT/s) to a second data rate below 64 GT/s;
activate forward error correction for the data blocks;
transmit the data blocks with forward error correction at the second data rate below 64 GT/s;
transmit skip ordered set (SKP OS) after the data blocks without forward error correction.
14. The system of claim 13 , the downstream circuitry to determine error correcting code (ECC) for the forward error correction for the data rate below 64 GT/s.
15. The system of claim 14 , the downstream circuitry to transmit a portion of the ECC for the data blocks on each lane of a link.
16. The system of claim 13 , the downstream circuitry to change the data rate from 64 GT/s to one of 32, 16, or 8 GT/s.
17. The system of claim 13 , the downstream circuitry to transmit a first set of SKP OS and transmitting a second, redundant set of SKP OS without forward error correction.
18. The system of claim 13 , the downstream circuitry to:
determine the second data rate for a link to operate that is lower than 64 GT/s;
cause the link to enter into a recovery state; and
change the data rate to the second data rate.
19. The system of claim 13 , further comprising:
an endpoint device comprising an upstream port comprising circuitry to receive data blocks across the link; and
a retimer connected downstream of the downstream port and upstream of the upstream port, the retimer to:
receive data blocks at the second data rate, the data blocks comprising error correcting code; and
transmit data blocks to the endpoint device with the error correcting code at the second data rate.
20. The system of claim 19 , wherein the retimer is to:
receive SKP OS without error correcting code; and
transmit SKP OS without error correcting code at the second data rate.