Granted Patent B2

US 12,242,336 · App. 18/456,059 · Granted Mar 4, 2025

Inventor: Debendra Das Sharma (Saratoga, CA)

Assignee: Intel Corporation

G06F11/10G06F13/4027

Abstract

Claims (40)

1. An apparatus comprising:

a port to couple to another device over an interconnect, wherein the port comprises physical layer (PHY) circuitry to support transport of flits of a plurality of different flit formats over the interconnect, the plurality of different flit formats have a plurality of different flit lengths, and the PHY circuitry comprises:

first cyclic redundancy check (CRC) circuitry to encode CRC values for flits of a first one of the plurality of different flit formats;

second CRC circuitry to encode CRC values for flits of a second one of the plurality of different flit formats; and

selection circuitry to:

identify one of the plurality of different flit formats to be applied to data to be sent on the interconnect; and

select one of the first CRC circuitry or the second CRC circuitry for use in association with generation of a flit associated with the data based on the identified one of the plurality of different flit formats.

2. The apparatus of claim 1 , wherein the PHY circuitry further comprises forward error correction (FEC) circuitry to encode FEC values for flits in at least a subset of the plurality of different flit formats.

3. The apparatus of claim 2 , wherein a FEC value generated by the FEC circuitry and a CRC value generated by the first CRC circuitry or the second CRC circuitry is to be included within the flit.

4. The apparatus of claim 1 , wherein CRC values generated by the first CRC circuitry have a different length than CRC values generated by the second CRC circuitry.

5. The apparatus of claim 1 , wherein the plurality of different flit formats comprise a plurality of flit formats supported by a particular interconnect protocol.

6. The apparatus of claim 5 , wherein the particular interconnect protocol comprises a Compute Express Link (CXL)-based protocol.

7. The apparatus of claim 1 , wherein the plurality of different flit formats correspond to a plurality of interconnect protocols.

8. The apparatus of claim 7 , wherein the plurality of interconnect protocols comprise a CXL-based protocol and a Peripheral Component Interconnect Express (PCle)-based protocol.

9. The apparatus of claim 7 , wherein the PHY circuitry supports transmission of data of the plurality of different protocols.

10. The apparatus of claim 9 , wherein the PHY circuitry supports multiplexing of data of the plurality of different protocols on a common PHY of the interconnect.

11. The apparatus of claim 1 , wherein the one of the plurality of different flit formats is identified during link training for the interconnect.

12. The apparatus of claim 1 , wherein the first CRC circuitry implements a GF(2∧8) CRC.

13. A method comprising:

identifying a plurality of flits received on an interconnect at a first device from a second device, wherein the plurality of flits comprises flits of a plurality of different flit formats, and the plurality of different flit formats have a plurality of different flits lengths;

determining that a particular one of the plurality of different flit formats applies to a particular one of the plurality of flits, wherein the particular flit comprises a cyclic redundancy check (CRC) value determined for the particular flit;

selecting one of first cyclic redundancy check (CRC) circuitry or second CRC circuitry of a physical layer of the first device to decode the particular flit based on the determined particular flit format; and

determining whether errors exist in the particular flit based on decoding of the CRC value.

14. A system comprising:

a first device; and

a second device coupled to the first device by an interconnect, wherein the second device comprises a port to interface with the interconnect, and the port comprises:

physical layer (PHY) circuitry to support transport of flits of a plurality of different flit formats over the interconnect, the plurality of different flit formats have a plurality of different flit lengths, and the PHY circuitry comprises:

first cyclic redundancy check (CRC) circuitry to encode CRC values for flits of a first one of the plurality of different flit formats;

second CRC circuitry to encode CRC values for flits of a second one of the plurality of different flit formats; and

selection circuitry to:

identify one of the plurality of different flit formats to be applied to data to be sent on the interconnect; and

select one of the first CRC circuitry or the second CRC circuitry for use in association with generation of a flit associated with the data based on the identified one of the plurality of different flit formats.

15. The system of claim 14 , wherein the second device comprises a processor device.

16. The system of claim 14 , wherein the second device comprises a hardware accelerator.

17. The system of claim 14 , wherein the second device comprises a memory device.

18. The system of claim 14 , wherein the plurality of different flit formats correspond to a plurality of interconnect protocols.

19. The system of claim 18 , wherein the plurality of interconnect protocols comprise a CXL-based protocol and a Peripheral Component Interconnect Express (PCle)-based protocol.

20. The system of claim 18 , wherein the PHY circuitry supports multiplexing of data of the plurality of different protocols on a common PHY of the interconnect.

21. The system of claim 14 , wherein the plurality of different flit formats comprise a plurality of flit formats supported by a CXL-based protocol.

22. The system of claim 14 , wherein the PHY circuitry further comprises forward error correction (FEC) circuitry to encode FEC values for flits in at least a subset of the plurality of different flit formats.

Continuity (3)

References Cited (212)