Arrangement and thermal management of 3D stacked dies
Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.
1. A semiconductor chip device, comprising:
a first semiconductor chip having a floor plan with a processor core portion having one or more processor cores and a second portion having logic other than a processor core;
at least one second semiconductor chip stacked on a side of the first semiconductor chip, on the second portion, and not on the processor core portion; and
a dummy component mounted on the same side of the first semiconductor chip, on the processor core portion for transferring heat therefrom, and not on the second portion.
2. The semiconductor chip device of claim 1 , comprising a thermal interface material layer positioned between the dummy component and the first semiconductor chip.
3. The semiconductor chip device of claim 2 , comprising a molding material at least partially encapsulating the dummy component and the at least one second semiconductor chip.
4. The semiconductor chip device of claim 3 , wherein the molding material does not cover an upper surface of the dummy component and an upper surface of the at least one second semiconductor chip.
5. The semiconductor chip device of claim 1 , wherein the dummy component comprises a block of silicon, copper, graphite, sapphire or diamond.
6. The semiconductor chip device of claim 1 , wherein the dummy component comprises a backside metallization.
7. The semiconductor chip device of claim 1 , comprising a heat spreader positioned on the at least one second semiconductor chip and the dummy component.
8. The semiconductor chip device of claim 1 , wherein the at least one second semiconductor chip comprises a memory chip.
9. The semiconductor chip device of claim 1 , wherein the first semiconductor chip floor plan includes another processor core portion having one or more processor cores, the semiconductor chip device including another dummy component mounted on the another processor core portion.
10. The semiconductor chip device of claim 1 , wherein the first semiconductor chip comprises plural I/O structures to electrically interface with another component.
11. An apparatus comprising:
a computer processor; and
computer memory coupled to the computer processor; wherein:
the computer processor comprises a printed circuit board that includes a processor chip having a floor plan with a processor core portion and a second portion, the processor core portion having one or more processor cores and the second portion having logic other than a processor core;
the computer memory comprises at least one memory chip stacked on a side of the processor chip, on the second portion and not on the processor core portion; and
a dummy component is mounted on the same side of the processor chip, on the processor core portion for transferring heat therefrom, and not on the second portion.
12. The apparatus of claim 11 , comprising a thermal interface material layer positioned between the dummy component and the processor chip.
13. The apparatus of claim 12 , comprising a molding material at least partially encapsulating the dummy component and the at least one memory chip.
14. The apparatus of claim 13 , wherein the molding material does not cover an upper surface of the dummy component and an upper surface of the at least one memory chip.
15. The apparatus of claim 11 , wherein the dummy component comprises a block of silicon, copper, graphite, sapphire or diamond.
16. The apparatus of claim 11 , wherein the dummy component comprises a backside metallization.
17. The apparatus of claim 11 , comprising a heat spreader positioned on the at least one memory chip and the dummy component.
18. The apparatus of claim 11 , wherein the processor chip floor plan includes another processor core portion having one or more processor cores, and another dummy component is mounted on the another processor core portion.
19. The apparatus of claim 11 , wherein the processor chip comprises plural I/O structures to electrically interface with another component.
20. The apparatus of claim 11 , wherein the second portion of the processor chip comprises one of: bus logic, input/output logic, and cache logic.