Compute-in-memory packages and methods forming the same

1. A method of forming an integrated circuit package, the method comprising:

placing a first plurality of dies over a carrier, wherein the first plurality of dies comprise at least a first logic die and a first memory die;

placing a second plurality of dies over the first plurality of dies, wherein the second plurality of dies are electrically coupled to the first plurality of dies, and wherein the second plurality of dies comprise at least a second logic die and a second memory die;

after the second plurality of dies are placed, forming a through-via extending into one of the second plurality of dies, wherein the through-via lands on a metal pad in the one of the second plurality of dies;

placing a third plurality of dies over the second plurality of dies, wherein the third plurality of dies are electrically coupled to the first plurality of dies and the second plurality of dies, and wherein the third plurality of dies comprise at least a third logic die and a third memory die; and

forming electrical connectors over and electrically coupling to the first plurality of dies, the second plurality of dies, and the third plurality of dies.

2. The method of claim 1 further comprising bonding the second plurality of dies to the first plurality of dies through direct dielectric bonding, wherein at a time of the direct dielectric bonding, the second plurality of dies are electrically de-coupled from the first plurality of dies.

3. The method of claim 1 further comprising filling a dielectric material between the second plurality of dies, wherein the dielectric material comprises a top portion overlapping the one of the plurality of dies, wherein the through-via penetrates through the top portion of the dielectric material.

4. The method of claim 1 further comprising:

filling a first dielectric material, wherein the first dielectric material continuously extends into gaps between the first plurality of dies and gaps between the second plurality of dies, wherein the first dielectric material has a portion covering the second plurality of dies;

forming metal pads over the first dielectric material;

forming a second dielectric material to cover the metal pads; and

bonding the third plurality of dies to the second dielectric material through dielectric-to-dielectric bonding.

5. The method of claim 1 , wherein one of the second plurality of dies is physically bonded to both a first one and a second one of the first plurality of dies.

6. The method of claim 5 further comprising forming a through-via physically connecting the one of the second plurality of dies to the first one of the first plurality of dies, and there is no direct electrical connection between the one of the second plurality of dies and the second one of the first plurality of dies.

7. The method of claim 1 , wherein the forming the electrical connectors comprises forming solder regions.

8. The method of claim 1 , wherein the forming the electrical connectors comprises:

forming a dielectric layer over the third plurality of dies; and

forming metal pillars in the dielectric layer, with top surfaces of the metal pillars being coplanar with a top surface of the dielectric layer.

9. The method of claim 1 further comprising:

performing a die-saw to form a plurality of packages, wherein the first plurality of dies, the second plurality of dies, and the third plurality of dies are in one of the plurality of packages.

10. The method of claim 9 further comprising:

bonding the one of the plurality of packages to a package component through flip-chip bonding; and

encapsulating the one of the plurality of packages in an encapsulant.

11. The method of claim 9 further comprising:

encapsulating the one of the plurality of packages in an encapsulant; and

forming redistribution lines and dielectric layers overlapping both the one of the plurality of packages and the encapsulant.

12. A method of forming an integrated circuit package, the method comprising:

placing first-tier dies;

bonding second-tier dies to the first-tier dies;

filling a first gap-filling dielectric material, wherein the first gap-filling dielectric material is filled into both gaps between the first-tier dies and gaps between the second-tier dies;

after the first gap-filling dielectric material is filled, forming first through-vias extending into the second-tier dies, wherein at least a lower portion of each of the first through-vias is inside one of the second-tier dies, and wherein the first through-vias electrically couple the second-tier dies to the first-tier dies;

forming metal pads over the first gap-filling dielectric material and electrically coupling to the first through-vias;

forming a dielectric layer covering the metal pads;

bonding third-tier dies to the dielectric layer, wherein each tier of the first-tier dies, second-tier dies, and the third-tier dies comprises at least a logic die and a memory die; and

forming second through-vias penetrating through the third-tier dies to electrically couple to the metal pads.

13. The method of claim 12 , wherein the first through-vias comprise a first through-via terminating in one of the second-tier dies, and a second through-via terminating in one of the first-tier dies.

14. The method of claim 12 , wherein the first gap-filling dielectric material comprises a top portion overlapping the second-tier dies, and each of the first through-vias penetrates through the top portion of the first gap-filling dielectric material.

15. The method of claim 12 , wherein one of the first through-vias penetrates through a metal pad in the second-tier dies to land on a metal pad on one of the first-tier dies.

16. A method of forming an integrated circuit package, the method comprising:

placing a first plurality of dies, wherein the first plurality of dies comprise a first device die;

bonding a second plurality of dies over the first plurality of dies, wherein the second plurality of dies comprise a second device die;

encapsulating the second plurality of dies in a gap-filling material;

planarizing the gap-filling material, wherein the gap-filling material has a top portion covering the second plurality of dies; and

after the gap-filling material is planarized, forming a first through-via penetrating through the second device die, wherein the first through-via electrically connects the second device die to the first device die.

17. The method of claim 16 , wherein the first through-via is stopped on a first metal pad in the first device die.

18. The method of claim 17 , wherein the first through-via penetrates through a second metal pad in the second device die, and wherein the first through-via is in physical contact with the second metal pad.

19. The method of claim 16 further comprising:

forming a second through-via penetrating through a semiconductor substrate of the second device die, wherein the second through-via is stopped on an additional metal pad in the second device die.

20. The method of claim 16 further comprising forming a third metal pad over and contacting the first through-via.

21. The method of claim 20 further comprising:

depositing a dielectric layer on the third metal pad;

bonding a third device die to the dielectric layer; and

forming an additional through-via penetrating through the third device die and the dielectric layer to contact the third metal pad.