IP Library › Granted Patent US 12,610,871
Granted Patent B2
US 12,610,871 · App. 18/365,999 · Granted Apr 21, 2026

Through-dielectric vias for direct connection and method forming same

Inventors: Ming-Fa Chen (Taichung City, TW); Chuan-An Cheng (Zhubei City, TW); Sung-Feng Yeh (Taipei City, TW); Chih-Chia Hu (Taipei City, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H01L25/0652H01L21/565H01L21/568H01L21/6835H01L21/76898H01L23/3128H01L23/481H01L23/5386H01L23/5389H01L24/08H01L24/80H01L25/50H01L2221/68372H01L2224/08145H01L2224/80006H01L2224/80895H01L2224/80896H01L2225/06541H01L2225/06548H01L2225/06586
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Quick Facts
Patent No.
US 12,610,871
App. No.
18/365,999
Granted
Apr 21, 2026
Kind
B2
Abstract

A method includes bonding a tier-1 device die to a carrier, forming a first gap-filling region to encapsulate the tier-1 device die, forming a first redistribution structure over and electrically connected to the tier-1 device die, and bonding a tier-2 device die to the tier-1 device die. The tier-2 device die is over the tier-1 device die, and the tier-2 device die extends laterally beyond a corresponding edge of the tier-1 device die. The method further includes forming a second gap-filling region to encapsulate the tier-2 device die, removing the carrier, and forming a through-dielectric via penetrating through the first gap-filling region. The through-dielectric via is overlapped by, and is electrically connected to, the tier-2 device die. A second redistribution structure is formed, wherein the first redistribution structure and the second redistribution structure are on opposing sides of the tier-1 device die.

Claims (58)

1 . A package comprising:

a first redistribution structure comprising:

a first dielectric layer continuously extending from a first edge to a second edge of the package, wherein the first edge and the second edge are opposing edges of the package; and

a first plurality of redistribution lines in the first dielectric layer;

a tier-1 device die over the first redistribution structure, wherein the tier-1 device die comprises:

a first semiconductor substrate; and

a first through-semiconductor via penetrating through the first semiconductor substrate;

a first gap-filling region encapsulating the tier-1 device die;

a second redistribution structure over and electrically connected to the tier-1 device die and the first through-semiconductor via, wherein the second redistribution structure comprises:

a second dielectric layer continuously extending from the first edge to the second edge of the package; and

a second plurality of redistribution lines in the second dielectric layer;

a tier-2 device die over and bonded to the tier-1 device die through conductive features in the second redistribution structure, wherein the tier-2 device die extends laterally beyond a corresponding edge of the tier-1 device die;

a second gap-filling region encapsulating the tier-2 device die;

a first through-dielectric via penetrating through the first gap-filling region, wherein the first through-dielectric via electrically connects the tier-2 device die to the first redistribution structure; and

a tier-3 device die over and bonded to the tier-2 device die, wherein the tier-3 device die comprises a die edge that forms a part of an outmost edge of the package.

2 . The package of claim 1 , wherein the first through-dielectric via is overlapped by the tier-2 device die.

3 . The package of claim 1 further comprising a second through-dielectric via penetrating through the first gap-filling region, the second redistribution structure, and the second gap-filling region.

4 . The package of claim 3 , wherein the second through-dielectric via comprises a portion continuously extending into the first gap-filling region, the second redistribution structure, and the second gap-filling region without interfaces therein.

5 . A package comprising:

a first redistribution structure;

a first device die over the first redistribution structure;

a first gap-filling region encapsulating the first device die;

a second device die over the first device die, wherein the second device die laterally extends beyond a first edge of the first device die;

a second gap-filling region encapsulating the second device die, wherein the second device die is inside the second gap-filling region;

a third device die over the second device die, wherein the third device die laterally extends beyond a second edge of the second device die, and wherein a third edge of the third device die forms a part of an outmost edge of the package;

a third gap-filling region contacting the third device die;

a first through-dielectric via in the first gap-filling region, wherein the first through-dielectric via is overlapped by, and is electrically connected to, the second device die; and

a second through-dielectric via overlapped by the third device die, wherein the second through-dielectric via penetrates through the first gap-filling region and the second gap-filling region.

6 . The package of claim 5 , wherein the second through-dielectric via comprises a portion continuously extending through the first gap-filling region and the second gap-filling region without interfaces therein.

7 . The package of claim 5 , wherein the second through-dielectric via has a first top end and a first bottom end wider than the first top end.

8 . The package of claim 7 , wherein the first through-dielectric via has a second top end and a second bottom end narrower than the second top end.

9 . The package of claim 1 , wherein top surfaces of the second gap-filling region and the tier-2 device die are coplanar, and bottom surfaces of the second gap-filling region and the tier-2 device die are coplanar.

10 . The package of claim 1 , wherein the second redistribution structure comprises a dielectric layer, and wherein a bottom surface of the dielectric layer contacts a first top surface of the first gap-filling region and a second top surface of the tier-1 device die.

11 . The package of claim 1 , wherein the second redistribution structure is higher than the tier-1 device die and lower than the tier-2 device die.

12 . The package of claim 5 further comprising a second redistribution structure over and contacting the first device die and the first gap-filling region, wherein conductive features in the second redistribution structure comprise a first metal pad joined to a second metal pad in the second device die.

13 . A package comprising:

a tier-1 device die, wherein the tier-1 device die comprises a semiconductor substrate and a first through-via penetrating through the semiconductor substrate;

a first gap-filling region, with the tier-1 device die being in the first gap-filling region;

a first dielectric layer over the tier-1 device die, wherein the first dielectric layer extends laterally beyond the tier-1 device die;

a first bond pad and a second bond pad in the first dielectric layer;

a tier-2 device die, wherein the first dielectric layer further extends laterally beyond the tier-2 device die, and the tier-2 device die comprising:

a second dielectric layer bonding to the first dielectric layer; and

a third bond pad in the second dielectric layer and bonding to the first bond pad;

a second gap-filling region, with the tier-2 device die being in the second gap-filling region; and

a second through-via in the first gap-filling region, with top surfaces of the second through-via and the first gap-filling region being coplanar, and bottom surfaces of the second through-via and the first gap-filling region being coplanar.

14 . The package of claim 13 , wherein the first dielectric layer extends to an edge of the package.

15 . The package of claim 13 further comprising a third through-via in the first gap-filling region, the first dielectric layer, and the second gap-filling region.

16 . The package of claim 13 further comprising:

a third dielectric layer over the tier-2 device die, wherein the third dielectric layer extends laterally beyond the tier-2 device die;

a fourth bond pad in the third dielectric layer;

a tier-3 device die comprising:

a fourth dielectric layer bonding to the third dielectric layer; and

a fifth bond pad bonding to the fourth bond pad; and

a third gap-filling region contacting the tier-3 device die to form a vertical interface.

17 . The package of claim 13 , wherein the second through-via is joined to a bottom surface of the second bond pad.

18 . The package of claim 13 further comprising a third through-via in the first gap-filling region and the second gap-filling region, with top surfaces of the third through-via and the second gap-filling region being coplanar, and bottom surfaces of the third through-via and the first gap-filling region being coplanar.

19 . The package of claim 16 , wherein the tier-3 device die comprises a first outmost edge forming a part of a second outmost edge of the package.

20 . The package of claim 5 , wherein the third gap-filling region contacts a fourth edge of the third device die, and wherein the third edge and the fourth edge are opposing outmost edges of the third device die.

Continuity (3)
Division 17229283 · Apr 13, 2021
Provisional Application 63148642 · Feb 12, 2021
Related Publication 20240021576A1 · Jan 18, 2024
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