Systems and methods to perform floating-point addition with selected rounding
Disclosed embodiments relate to performing floating-point addition with selected rounding. In one example, a processor includes circuitry to decode and execute an instruction specifying locations of first and second floating-point (FP) sources, and an opcode indicating the processor is to: bring the FP sources into alignment by shifting a mantissa of the smaller source FP operand to the right by a difference between their exponents, generating rounding controls based on any bits that escape; simultaneously generate a sum of the FP sources and of the FP sources plus one, the sums having a fuzzy-Jbit format having an additional Jbit into which a carry-out, if any, select one of the sums based on the rounding controls, and generate a result comprising a mantissa-wide number of most-significant bits of the selected sum, starting with the most significant non-zero Jbit.
1. A processor comprising:
decode circuitry to decode an instruction specifying locations of first and second floating-point (FP) sources, and an opcode indicating execution circuitry is to:
shift a mantissa of the smaller source FP operand to the right until the FP sources are aligned, generating rounding controls based on any bits that escape,
generate four sums comprising a first sum of the FP sources on a first range, a second sum of the FP sources plus one on the first range, a third sum of the FP sources on a second different range, and a fourth sum of the FP sources plus one on the second different range, the sums having a fuzzy-Jbit format with an additional possible Jbit position,
select one of the four sums based on the rounding controls, and
generate a result comprising a mantissa-wide number of most-significant bits of the selected sum, starting with the most significant non-zero Jbit; and
the execution circuitry to execute the instruction as per the opcode.
2. The processor of claim 1 , wherein the instruction is further to specify locations of a third and a fourth source FP operand, and the opcode further indicates the execution circuitry, in a first cycle, is to generate a product of the third and fourth source FP operands, the product to be used in a second cycle by serving as a first source FP format to be used in generating the result.
3. The processor of claim 2 , wherein the first, second, and third FP operands comprise packed-data vectors having multiple floating-point elements, and wherein the execution circuitry is to execute the decoded instruction on each of the multiple elements in parallel.
4. The processor of claim 2 , wherein the first, second, and third FP operands comprise matrices having M rows by N columns of floating-point elements, and wherein the execution circuitry is to execute the decoded instruction on a subset of the M×N elements in parallel.
5. The processor of claim 1 , wherein the first and second FP operands have different signs.
6. The processor of claim 1 , wherein the fuzzy-Jbit format, consistent with a standard format promulgated by the Institute of Electronics and Electrical Engineers (IEEE-754), comprises a 23-bit fraction and 9-bit exponent, but, unlike the IEEE 754 standard, which defines bit 23 as a location of the Jbit, the fuzzy-Jbit format has multiple possible locations for the Jbit.
7. The processor of claim 1 , wherein the result, maintaining its fuzzy-Jbit format, is routed for use by a subsequent floating-point operation.
8. The processor of claim 1 , wherein the execution circuitry is to convert the result into standard IEEE 754 format and write the converted result into a destination operand further specified by the instruction.
9. A method to be performed by a processor, the method comprising:
decoding, using decode circuitry, an instruction specifying locations of first and second floating-point (FP) sources, and an opcode indicating execution circuitry is to:
shift a mantissa of the smaller source FP operand to the right until the FP sources are aligned, generating rounding controls based on any bits that escape,
generate four sums comprising a first sum of the FP sources on a first range, a second sum of the FP sources plus one on the first range, a third sum of the FP sources on a second different range, and a fourth sum of the FP sources plus one on the second different range, the sums having a fuzzy-Jbit format with an additional possible Jbit position,
select one of the four sums based on the rounding controls, and
generate a result comprising a mantissa-wide number of most-significant bits of the selected sum, starting with the most significant non-zero Jbit; and
executing, using the execution circuitry, the instruction as per the opcode.
10. The method of claim 9 , wherein the instruction is further to specify locations of a third and a fourth source FP operands, and the opcode further indicates the execution circuitry, in a first cycle, is to generate a product of the third and fourth source FP operands, the product to be used in a second cycle by serving as a first source FP format to be used in generating the result.
11. The method of claim 10 , wherein the first, second, and third FP operands comprise packed-data vectors having multiple floating-point elements, and wherein the execution circuitry is to execute the decoded instruction on each of the multiple elements in parallel.
12. The method of claim 10 , wherein the first, second, and third FP operands comprise matrices having M rows by N columns of floating-point elements, and wherein the execution circuitry is to execute the decoded instruction on a subset of the M×N elements in parallel.
13. The method of claim 9 , wherein the first and second FP operands have different signs.
14. The method of claim 9 , wherein the fuzzy-Jbit format, consistent with a standard format promulgated by the Institute of Electronics and Electrical Engineers (IEEE-754), comprises a 23-bit fraction and 9-bit exponent, but, unlike the IEEE 754 standard, which defines bit 23 as a location of the Jbit, the fuzzy-Jbit format has multiple possible locations for the Jbit.
15. The method of claim 9 , wherein the result, maintaining its fuzzy-Jbit format, is routed for use by a subsequent floating-point operation.
16. The method of claim 9 , wherein the execution circuitry is to convert the result into standard IEEE 754 format and write the converted result into a destination operand further specified by the instruction.
17. A non-transitory machine readable medium containing code to which a processor is to respond by:
decoding, using decode circuitry, an instruction specifying locations of first and second floating-point (FP) sources, and an opcode indicating execution circuitry is to:
shift a mantissa of the smaller source FP operand to the right until the FP sources are aligned, generating rounding controls based on any bits that escape,
generate four sums comprising a first sum of the FP sources on a first range, a second sum of the FP sources plus one on the first range, a third sum of the FP sources on a second different range, and a fourth sum of the FP sources plus one on the second different range, the sums having a fuzzy-Jbit format with an additional possible Jbit position;
select one of the four sums based on the rounding controls, and
generate a result comprising a mantissa-wide number of most-significant bits of the selected sum, starting with the most significant non-zero Jbit; and
executing, using the execution circuitry, the instruction as per the opcode.
18. The non-transitory machine readable medium of claim 17 , wherein the instruction is further to specify locations of a third and a fourth source FP operand, and the opcode further indicates the execution circuitry, in a first cycle, is to generate a product of the third and fourth source FP operands, the product to be used in a second cycle by serving as a first source FP format to be used in generating the result.
19. The non-transitory machine readable medium of claim 17 , wherein the first and second FP operands have different signs.
20. The non-transitory machine readable medium of claim 17 , wherein the fuzzy-Jbit format, consistent with a standard format promulgated by the Institute of Electronics and Electrical Engineers (IEEE-754), comprises a 23-bit fraction and 9-bit exponent, but, unlike the IEEE 754 standard, which defines bit 23 as a location of the Jbit, the fuzzy-Jbit format has multiple possible locations for the Jbit.