Dual sum of quadword 16×16 multiply and accumulate
Techniques for matrix multiplication are described. In some examples, a single instruction having a format of fields for an opcode, one or more fields to indicate a location of a source/destination operand, one or more fields to indicate a location of a first source operand, and one or more fields to indicate a location of a second source operand is used. Wherein the opcode is to indicate that execution circuitry is to: multiply values from corresponding data elements of the first and second sources, add a first subset of the multiplied values to a first value from the source/destination operand and store in a first data element position of the source/destination operand, and add a second subset of the multiplied values to a second value from the source/destination operand and store in a second data element position of the source/destination operand.
1. An apparatus comprising:
decoder circuitry to decode a single instruction, wherein the single instruction is to include fields for an opcode, one or more fields to indicate a location of a source/destination operand, one or more fields to indicate a location of a first source operand, and one or more fields to indicate a location of a second source operand, wherein the opcode is to indicate that execution circuitry is to:
multiply values from corresponding data elements of the first and second sources,
add a first subset of the multiplied values to a first value from the source/destination operand and store in a first data element position of the source/destination operand, and
add a second subset of the multiplied values to a second value from the source/destination operand and store in a second data element position of the source/destination operand; and
execution circuitry to execute the decoded instruction according to the opcode.
2. The apparatus of claim 1 , wherein the field for the identifier of the first source operand is to identify a vector register.
3. The apparatus of claim 1 , wherein the field for the identifier of the first source operand is to identify a memory location.
4. The apparatus of claim 1 , wherein the opcode is to indicate data elements of the first source operand are signed and data elements of the second source are unsigned.
5. The apparatus of claim 1 , wherein the data elements of the first and second source operands at 16-bit integer values.
6. The apparatus of claim 5 , wherein the data elements of the source/destination operand are 64-bit integer values.
7. The apparatus of claim 1 , wherein the opcode is to indicate data element sizes of the first and second source operands and the source/destination operand.
8. A non-transitory machine-readable medium storing an instance of a single instruction which when processed by a machine is to cause the machine to perform a method comprising:
decoding the single instruction, wherein the single instruction is to include fields for an opcode, one or more fields to indicate a location of a source/destination operand, one or more fields to indicate a location of a first source operand, and one or more fields to indicate a location of a second source operand, wherein the opcode is to indicate that execution circuitry is to:
multiply values from corresponding data elements of the first and second sources,
add a first subset of the multiplied values to a first value from the source/destination operand and store in a first data element position of the source/destination operand, and
add a second subset of the multiplied values to a second value from the source/destination operand and store in a second data element position of the source/destination operand; and
executing the decoded instruction according to the opcode.
9. The non-transitory machine-readable medium of claim 8 , wherein the field for the identifier of the first source operand is to identify a vector register.
10. The non-transitory machine-readable medium of claim 8 , wherein the field for the identifier of the first source operand is to identify a memory location.
11. The non-transitory machine-readable medium of claim 8 , wherein the opcode is to indicate data elements of the first source operand are signed and data elements of the second source are unsigned.
12. The non-transitory machine-readable medium of claim 8 , wherein the data elements of the first and second source operands at 16-bit integer values.
13. The non-transitory machine-readable medium of claim 12 , wherein the data elements of the source/destination operand are 64-bit integer values.
14. The non-transitory machine-readable medium of claim 8 , wherein the opcode is to indicate data element sizes of the first and second source operands and the source/destination operand.
15. A non-transitory machine-readable medium storing an instance of a single instruction which when processed by a machine is to cause the machine to perform a method comprising:
translating the single instruction from a first instruction set architecture to one or more instructions of a second instruction set architecture, wherein the single instruction is to include fields for an opcode, one or more fields to indicate a location of a source/destination operand, one or more fields to indicate a location of a first source operand, and one or more fields to indicate a location of a second source operand, wherein the opcode is to indicate that execution circuitry is to:
multiply values from corresponding data elements of the first and second sources,
add a first subset of the multiplied values to a first value from the source/destination operand and store in a first data element position of the source/destination operand, and
add a second subset of the multiplied values to a second value from the source/destination operand and store in a second data element position of the source/destination operand;
decoding the one or more instructions of the second instruction set architecture; and
executing the decoded one or more instructions according to the opcode of the single instruction.
16. The non-transitory machine-readable medium of claim 15 , wherein the field for the identifier of the first source operand is to identify a vector register.
17. The non-transitory machine-readable medium of claim 15 , wherein the field for the identifier of the first source operand is to identify a memory location.
18. The non-transitory machine-readable medium of claim 15 , wherein the opcode is to indicate data elements of the first source operand are signed and data elements of the second source are unsigned.
19. A system comprising:
a processor comprising:
decoder circuitry to decode a single instruction, wherein the single instruction is to include fields for an opcode, one or more fields to indicate a location of a source/destination operand, one or more fields to indicate a location of a first source operand, and one or more fields to indicate a location of a second source operand, wherein the opcode is to indicate that execution circuitry is to:
multiply values from corresponding data elements of the first and second sources,
add a first subset of the multiplied values to a first value from the source/destination operand and store in a first data element position of the source/destination operand, and
add a second subset of the multiplied values to a second value from the source/destination operand and store in a second data element position of the source/destination operand, and
execution circuitry to execute the decoded instruction according to the opcode; and
memory to store the single instruction.
20. The system of claim 19 , wherein the opcode is to indicate data elements of the first source operand are signed and data elements of the second source are unsigned.