System and method for background calibration of time interleaved ADC

1. A method for Background Calibration of Time Interleaved ADC comprising:

sampling a common input signal, said sampling is performed by an array of sub analog to digital converters, each generating individual digital analog equivalent outputs with sampling time errors, said digital analog equivalent outputs are fed to sampling time error estimation circuitry to calculate a digital output proportional to sampling time error between two consecutive channels, without any restriction on input signal or ADC channel design, said sampling time error estimation circuitry composed of generating a delayed output of one of the two consecutive ADC channels, channel first and channel second and subtracting the said delayed output with digital output of the said second channel and producing the first subtracted output and output of said second channel subtracted with said first channel output delayed by sampling delay between the two consecutive channels and producing the second subtracted delayed output, absolute value of the said first subtracted output and said second subtracted delayed output is monitored for peak value of both for a fixed time duration and then subtracted values of the said peak values are the estimation of sampling time error between the said two consecutive channels which is used to change the sampling delay of the ADC channel such that skew error is reduced, wherein the method for background calibration of time interleaved ADC is repeated to each consecutive ADC channels of the said ADC array until the said skew error is below ADC resolution.

2. The method of claim 1 /as claimed in claim 1 further comprising a relative error calculator from first ADC channel to last the last ADC channel in the array.

3. The method of claim 1 /as claimed in claim 1 further comprising a feedback to the sampling time estimation circuitry in the order to reduce said sampling time errors and process is continued until said timing error is reduced to below ADC resolution.

4. The method of claim 2 /as claimed in claim 2 further comprising a digitally controlled delay element associated with each ADC channel in the array to modify the sampling time in proportion to the said estimated sampling error along with sign from the reference sampling point.

5. The method of claim 1 /as claimed in claim 1 wherein the background calibration of time interleaved ADC is performed without interrupting the ADC conversion process.

6. A system for background calibration of time interleaved ADC comprising:

an analog to digital converter (ADC) comprising a plurality of sub ADCs being configured to sample a common input signal and each generating individual digital analog equivalent outputs with sampling time errors;

a skew estimator configured to receive said individual digital analog equivalent outputs with the sampling time errors and to estimate the sampling time errors without requiring any specific restriction on the common input signal, wherein the skew estimator further comprises:

subtractors;

peak detectors;

delay elements configured to align channels data to calculate a digital output proportional to the sampling time errors between two consecutive channels subject to the subtractors and the peak detectors; and

an absolute element without any restriction on ADC channel design; and

a digitally controlled delay element configured to receive an output of the skew estimator and also being coupled with the common input signal to change a sampling clock delay to minimize the sampling time errors.