Integrated pixel and two-terminal non-volatile memory cell and an array of cells for deep in-sensor, in-memory computing

1. An integrated pixel and memory cell comprising:

a select transistor;

a two-terminal non-volatile memory device; and

a pixel comprising:

a reset transistor connected to a first voltage rail;

a photodiode connected in series with the reset transistor;

a sense node at a junction between the reset transistor and the photodiode; and

an amplifying transistor connected in series with the two-terminal non-volatile memory device and the select transistor between a second voltage rail that is different from the first voltage rail and a bitline, wherein the amplifying transistor has a gate electrically connected to the sense node.

2. The integrated pixel and memory cell of claim 1 , wherein the two-terminal non-volatile memory device comprises any of a magnetic tunnel junction device, a phase change memory device, and a memristor.

3. The integrated pixel and memory cell of claim 1 ,

wherein the cell is selectively operable in a write mode, a read mode and a functional computing mode,

wherein, during the write mode, a first data value is stored in the two-terminal non-volatile memory device, and

wherein, during the functional computing mode, the photodiode performs a light sensing process resulting in a second data value on the sense node and a combined data value that is a function of the first data value and the second data value read from the cell.

4. The integrated pixel and memory cell of claim 1 , wherein the second voltage rail comprises an adjustable voltage rail and wherein the two-terminal non-volatile memory device is in series between any of the following:

the amplifying transistor and the select transistor;

the second voltage rail and the amplifying transistor; and

the select transistor and the bitline.

5. The integrated pixel and memory cell of claim 1 , further comprising a switch that selectively electrically connects the gate of the amplifying transistor to the sense node.

6. The integrated pixel and memory cell of claim 1 ,

wherein the two-terminal non-volatile memory device comprises a first terminal connected to the amplifying transistor and a second terminal connected to the select transistor, and

wherein each cell further comprises an additional transistor connected to the second terminal.

7. The integrated pixel and memory cell of claim 1 ,

wherein the bitline is for a column in an array of integrated pixel and memory cells, and

wherein a gate of the select transistor is connected to a wordline for a row in the array.

8. The integrated pixel and memory cell of claim 7 , further comprising an additional non-volatile memory device and an additional select transistor connected in series between the amplifying transistor and an additional bitline for the column, wherein a gate of the additional select transistor is connected to an additional wordline for the row.

9. The integrated pixel and memory cell of claim 7 , further comprising an additional non-volatile memory device and an additional select transistor connected in series between the amplifying transistor and an additional bitline for the column, wherein a gate of the additional select transistor is connected the wordline for the row.

10. The integrated pixel and memory cell of claim 7 , further comprising an additional select transistor connected in series between the amplifying transistor and an additional bitline for the column, wherein a gate of the additional select transistor is connected to an additional wordline for the row.

11. An integrated circuit structure comprising:

an array of integrated pixel and two-terminal non-volatile memory cells;

bitlines connected to columns of the cells in the array; and

wordlines connected to rows of cells in the array,

wherein each cell comprises:

a select transistor having a gate electrically connected to a wordline for a row;

a two-terminal non-volatile memory device; and

a pixel comprising:

a reset transistor;

a photodiode, wherein the reset transistor is connected in series between a first voltage rail and the photodiode;

a sense node at a junction between the reset transistor and the photodiode; and

an amplifying transistor, wherein the amplifying transistor the two-terminal non-volatile memory device and the select transistor are connected in series between an adjustable second voltage rail and a bitline for a column and wherein the amplifying transistor has a gate electrically connected to the sense node.

12. The integrated circuit structure of claim 11 , wherein the two-terminal non-volatile memory device comprises any of a magnetic tunnel junction, a phase change memory device, and a memristor.

13. The integrated circuit structure of claim 11 , further comprising a sensing circuit comprising transimpedance amplifiers for the columns, respectively, wherein each specific transimpedance amplifier for each specific column has a first input electrically connected to ground, a second input electrically connected to a specific bitline of the specific column and an output electrically connected to the specific bitline for the specific column.

14. The integrated circuit structure of claim 13 , the sensing circuit further comprising analog-to-digital converters for the columns, respectively, wherein each specific analog-to-digital converter for each specific column is electrically connected to the output of the specific transimpedance amplifier.

15. The integrated circuit structure of claim 11 ,

wherein the cells are selectively operable in a write mode, a read mode and a functional computing mode,

wherein, during the write mode in a specific cell in a specific row and a specific column, the reset transistor and the select transistor of the specific cell are turned on and specific bias conditions are applied to the adjustable second voltage rail and to a specific bitline for the specific column in order to store a first data value in the two-terminal non-volatile memory device of the specific cell,

wherein, during the functional computing mode in the specific cell,

the sense node of the specific cell is pre-charge,

a light sensing process is performed, wherein the photodiode of the pixel of the specific cell is exposed to light resulting in a second data value on the sense node,

following the light sensing process, the select transistor is turned on, and

a given electrical parameter is sensed on the specific bitline for the specific column,

wherein any change in the given electrical parameter on the specific bitline is indicative of a product of the first data value and the second data value in the specific cell, and

wherein a total change in the given electrical parameter on the specific bitline when multiple cells in the specific column concurrently operate in the functional computing mode is indicative of a result of a dot product computation.

16. The integrated circuit structure of claim 15 , wherein the given electrical parameter comprises any of a bitline voltage and a bitline current of the specific bitline.

17. A method comprising:

operating integrated pixel and two-terminal non-volatile memory cells in an array of the cells,

wherein an integrated circuit structure comprises: the array of the cells; bitlines connected to columns of the cells in the array; and wordlines connected to rows of cells in the array,

wherein each cell in the array comprises:

a select transistor having a gate electrically connected to a wordline for a row;

a two-terminal non-volatile memory device; and

a pixel comprising:

a reset transistor;

a photodiode, wherein the reset transistor is connected in series between a first voltage rail and the photodiode;

a sense node at a junction between the reset transistor and the photodiode; and

an amplifying transistor, wherein the amplifying transistor, the two-terminal non-volatile memory device, and the select transistor are connected in series between an adjustable second voltage rail and a bitline for a column and wherein the amplifying transistor has a gate electrically connected to the sense node, and

wherein the operating comprises operating the cells in the array in any of a write mode, a read mode, and a functional computing mode.

18. The method of claim 17 , wherein the two-terminal non-volatile memory device comprises any of a magnetic tunnel junction device, a phase change memory device, and a memristor.

19. The method of claim 17 , further comprising operating a specific cell in a specific row and a specific column in the write mode, wherein the operating of the specific cell in the specific row and the specific column in the write mode comprises:

turning on the reset transistor and the select transistor of the specific cell; and

applying specific bias conditions to the adjustable second voltage rail and to a specific bitline for the specific column in order to store a first data value in the two-terminal non-volatile memory device of the specific cell.

20. The method of claim 17 , further comprising operating a specific cell in a specific row and a specific column in the functional computing mode, wherein the operating of the specific cell in the specific row and the specific column in the functional computing mode comprises:

pre-charging a sense node of the specific cell;

performing a light sensing operation, wherein the photodiode of the pixel of the specific cell is exposed to light resulting in a second data value on the sense node;

turning on the select transistor; and

sensing a given electrical parameter on a specific bitline for the specific column,

wherein the given electrical parameter comprises any of a bitline voltage and a bitline current,

wherein any change in the given electrical parameter on the specific bitline is indicative of a product of a first data value stored in the two-terminal non-volatile memory device of the specific cell and the second data value on the sense node of the specific cell, and

wherein a total change the given electrical parameter in response to multiple cells in the specific column concurrently operating in the functional computing mode is indicative of a result of a dot product computation.