Double sided NMOS/PMOS structure and methods of forming the same
A chip includes a dielectric layer having a top surface and a bottom surface, a first semiconductor layer overlying and bonded to the top surface of the dielectric layer, and a first Metal Oxide-Semiconductor (MOS) transistor of a first conductivity type. The first MOS transistor includes a first gate dielectric overlying and contacting the first semiconductor layer, and a first gate electrode overlying the first gate dielectric. A second semiconductor layer is underlying and bonded to the bottom surface of the dielectric layer. A second MOS transistor of a second conductivity type opposite to the first conductivity type includes a second gate dielectric underlying and contacting the second semiconductor layer, and a second gate electrode underlying the second gate dielectric.
1. A method comprising:
forming a first transistor at a surface of a first semiconductor layer of a substrate;
performing a hydrogen implantation, wherein hydrogen ions penetrate through the first transistor and form a hydrogen-concentrated layer in a bulk semiconductor region, with the bulk semiconductor region being under the first semiconductor layer;
performing a cleaving process to separate the bulk semiconductor region into a second semiconductor layer and a third semiconductor layer, wherein the second semiconductor layer remains being in the substrate after the cleaving process;
forming a second transistor on the second semiconductor layer; and
forming a through-via electrically intercoupling the first transistor and the second transistor, wherein the through-via is encircled by an isolation layer, and the isolation layer contacts a source/drain region in one of the first transistor and the second transistor.
2. The method of claim 1 further comprising performing a planarization process on the second semiconductor layer after the cleaving process.
3. The method of claim 1 further comprising:
attaching the substrate to a carrier; and
forming a source/drain silicide region at a surface of a source/drain region of the second transistor, wherein the first transistor is between the source/drain silicide region and the carrier.
4. The method of claim 1 , wherein the first transistor and the second transistor are of opposite conductivity types.
5. The method of claim 1 , wherein the through-via comprises a first portion level with the first transistor, and a second portion level with the second transistor.
6. The method of claim 5 , wherein the isolation layer further contacts a dielectric region in one of the first semiconductor layer and the second semiconductor layer.
7. The method of claim 5 , wherein the first portion of the through-via is wider than the second portion of the through-via.
8. A method comprising:
forming first isolation regions penetrating through a first semiconductor layer to contact a buried isolation layer, wherein the buried isolation layer is further overlying a semiconductor region;
forming a first transistor based on a first active region in the first semiconductor layer;
forming a dielectric layer covering the first transistor;
performing a hydrogen implantation, wherein a hydrogen-concentrated layer is formed to separate the semiconductor region into a second semiconductor layer and a third semiconductor layer, wherein the second semiconductor layer contacts the buried isolation layer;
removing the hydrogen-concentrated layer and the third semiconductor layer from the second semiconductor layer;
forming second isolation regions penetrating through the second semiconductor layer to contact the buried isolation layer;
forming a second transistor based on a second active region in the second semiconductor layer; and
forming a through-via electrically intercoupling the first transistor and the second transistor, wherein the through-via is encircled by an isolation ring, and the isolation ring physically contacts a source/drain region of one of the first transistor and the second transistor.
9. The method of claim 8 , wherein the removing the hydrogen-concentrated layer and the third semiconductor layer comprises, after the hydrogen implantation, performing a cleaving process to mechanically separate the second semiconductor layer from the third semiconductor layer.
10. The method of claim 9 , wherein the cleaving process is performed when the dielectric layer is on the first transistor.
11. The method of claim 8 further comprising, after the hydrogen implantation, performing a planarization process on the second semiconductor layer, wherein the second isolation regions are formed after the second semiconductor layer is planarized.
12. The method of claim 8 , wherein a first source region and a first drain region of the first transistor contacts the buried isolation layer.
13. The method of claim 12 , wherein a second source region and a second drain region of the second transistor contacts the buried isolation layer.
14. The method of claim 8 , wherein a first gate of the first transistor overlaps a second gate of the second transistor.
15. The method of claim 8 , wherein the first semiconductor layer and the second semiconductor layer have different surface orientations.
16. A method comprising:
forming first isolation regions penetrating through a first semiconductor layer to contact a buried isolation layer;
forming a first transistor on the first semiconductor layer;
forming a dielectric layer covering the first transistor;
after the first transistor is covered with the dielectric layer, thinning a semiconductor region underlying the buried isolation layer to form a second semiconductor layer, wherein the second semiconductor layer contacts the buried isolation layer;
forming second isolation regions penetrating through the second semiconductor layer to contact the buried isolation layer;
forming a second transistor on the second semiconductor layer;
interconnecting the first transistor and the second transistor;
forming a first source/drain silicide region on a surface of a first source/drain region of the first transistor, wherein the first source/drain silicide region is formed after the second transistor is formed; and
forming a second source/drain silicide region on a surface of a second source/drain region of the second transistor.
17. The method of claim 16 , wherein the interconnecting comprises forming a through-via to connect the first transistor to the second transistor, wherein the through-via comprises a first portion level with the first transistor, and a second portion level with the second transistor.
18. The method of claim 17 , wherein the forming the through-via comprises etching the dielectric layer, the buried isolation layer, and at least one of the first isolation regions and the second isolation regions.
19. The method of claim 18 , wherein the through-via is encircled by an isolation layer, and the isolation layer comprises a first portion penetrating through the first semiconductor layer, and a second portion penetrating through one of the first isolation regions.
20. The method of claim 16 , wherein the interconnecting the first transistor and the second transistor comprises:
forming a through-via comprising a first portion extending into one of the first isolation regions and a second portion extending into one of the second isolation regions, wherein the through-via is encircled by an isolation ring, and wherein the isolation ring contacts a sidewall of one of the first source/drain region and the second source/drain region.