Semiconductor packages having package-on-package (PoP) structures

1. A semiconductor package comprising:

a lower semiconductor package; and

an upper semiconductor package on the lower semiconductor package,

wherein the upper semiconductor package comprises:

an upper package substrate;

a memory chip on the upper package substrate;

a wire that electrically connects the memory chip to the upper package substrate;

a power connector in the upper semiconductor package;

a signal connector on a bottom surface of the upper package substrate; and

an upper package molding material,

wherein a portion of the power connector is exposed from the upper package molding material at a top surface of the upper semiconductor package, and

wherein the portion of the power connector comprises at least a portion positioned higher than the memory chip.

2. The semiconductor package according to claim 1 , wherein the lower semiconductor package comprises:

a lower package substrate;

an application processor (AP) chip on the lower package substrate;

a lower package molding material on the lower package substrate and on the AP chip; and

a through-mold via (TMV) in the lower package molding material, and

wherein the lower package substrate comprises an internal signal wiring line, an external signal wiring line, and a lower package power wiring line.

3. The semiconductor package according to claim 2 , wherein the external signal wiring line and/or the lower package power wiring line electrically connects the AP chip to a solder on a bottom surface of the lower package substrate.

4. The semiconductor package according to claim 2 , further comprising an interposer between the lower semiconductor package and the signal connector,

wherein the interposer comprises an interposer bump, and

wherein an upper end of the TMV is in contact with the interposer bump.

5. The semiconductor package according to claim 1 , wherein the memory chip comprises a lower memory chip and an upper memory chip on the lower memory chip,

wherein the wire comprises a signal wire and a power wire,

wherein the upper package substrate comprises an upper chip signal wiring line, a lower chip signal wiring line, and a memory chip power wiring line,

wherein the signal wire is electrically connected to the upper memory chip, and

wherein the upper chip signal wiring line electrically connects the signal wire to the signal connector.

6. The semiconductor package according to claim 1 , wherein the memory chip comprises a lower memory chip and an upper memory chip on the lower memory chip,

wherein the wire comprises a signal wire and a power wire,

wherein the upper package substrate comprises an upper chip signal wiring line, a lower chip signal wiring line, and a memory chip power wiring line,

wherein the signal wire is electrically connected to the lower memory chip, and

wherein the lower chip signal wiring line electrically connects the signal wire to the signal connector.

7. The semiconductor package according to claim 1 , wherein the memory chip comprises a lower memory chip and an upper memory chip on the lower memory chip,

wherein the wire comprises a signal wire and a power wire,

wherein the upper package substrate comprises an upper chip signal wiring line, a lower chip signal wiring line, and a memory chip power wiring line,

wherein the power wire comprises a first power wire that is electrically connected to the upper memory chip and a second power wire that is electrically connected to the lower memory chip, and

wherein the memory chip power wiring line electrically connects the first power wire to the second power wire.

8. The semiconductor package according to claim 1 , wherein the memory chip comprises a lower memory chip and an upper memory chip on the lower memory chip,

wherein the wire comprises a signal wire and a power wire,

wherein the upper package substrate comprises a signal wiring line and a memory chip power wiring line,

wherein the signal wiring line electrically connects the signal wire to the signal connector, and

wherein the memory chip power wiring line electrically connects the power wire to the power connector.

9. A semiconductor system, comprising:

a lower board;

an upper board;

a lower semiconductor package on the lower board; and

an upper semiconductor package on the lower semiconductor package,

wherein the lower semiconductor package comprises:

a lower package substrate;

an application processor (AP) chip on the lower package substrate;

a lower package molding material on the lower package substrate and on the AP chip; and

a through-mold via (TMV) in the lower package molding material,

wherein the upper semiconductor package comprises:

an upper package substrate;

a memory chip on the upper package substrate;

a wire that electrically connects the memory chip to the upper package substrate;

a power connector on a top surface of the upper semiconductor package;

a power bump on the power connector;

a signal connector on a bottom surface of the upper package substrate; and

an upper package molding material,

wherein a gap between a bottom surface of the upper board and the top surface of the upper semiconductor package is less than 300 μm,

wherein a gap between a bottom surface of the upper semiconductor package and a top surface of the lower semiconductor package is less than 300 μm, and

wherein a gap between a bottom surface of the lower semiconductor package and a top surface of the lower board is less than 300 μm.

10. The semiconductor system according to claim 9 , wherein the lower package substrate comprises an internal signal wiring line, an external signal wiring line, and a lower package power wiring line, and

wherein the internal signal wiring line electrically connects the TMV to the AP chip.

11. The semiconductor system according to claim 9 , wherein the lower package substrate comprises an internal signal wiring line, an external signal wiring line, and a lower package power wiring line, and

wherein the external signal wiring line and/or the lower package power wiring line electrically connects the AP chip to a solder on a bottom surface of the lower package substrate.

12. The semiconductor system according to claim 9 , wherein the memory chip comprises a lower memory chip and an upper memory chip on the lower memory chip,

wherein the wire comprises a signal wire and a power wire, and

wherein the upper package substrate comprises an upper chip signal wiring line, a lower chip signal wiring line, and a memory chip power wiring line.

13. The semiconductor system according to claim 12 , wherein the signal wire is electrically connected to the upper memory chip, and

wherein the upper chip signal wiring line electrically connects the signal wire to the signal connector.

14. The semiconductor system according to claim 12 , wherein the signal wire is electrically connected to the lower memory chip, and

wherein the lower chip signal wiring line electrically connects the signal wire to the signal connector.

15. The semiconductor system according to claim 12 , wherein the power wire is electrically connected to the upper memory chip, and

wherein the memory chip power wiring line electrically connects the power wire to another power wire that is electrically connected to the lower memory chip.

16. A semiconductor package, comprising:

a lower semiconductor package; and

an upper semiconductor package on the lower semiconductor package,

wherein the upper semiconductor package comprises:

an upper package substrate;

a semiconductor chip on the upper package substrate;

an upper package molding material on the upper package substrate and the semiconductor chip;

a power connector extending vertically in the upper package molding material between a top surface of the upper semiconductor package and the semiconductor chip; and

a signal connector between the upper package substrate and the lower semiconductor package.

17. The semiconductor package according to claim 16 , wherein the semiconductor chip on the upper semiconductor package is a second semiconductor chip, wherein the lower semiconductor package comprises:

a lower package substrate;

a first semiconductor chip on the lower package substrate;

a lower package molding material on the lower package substrate and on the first semiconductor chip; and

a through-mold via (TMV) in the lower package molding material, and

wherein the lower package substrate comprises an internal signal wiring line, an external signal wiring line, and a lower package power wiring line.

18. The semiconductor package according to claim 17 , wherein the external signal wiring line and/or the lower package power wiring line electrically connects the first semiconductor chip to a solder on a bottom surface of the lower package substrate.

19. The semiconductor package according to claim 16 , wherein the semiconductor chip comprises a lower semiconductor chip and an upper semiconductor chip on the lower semiconductor chip,

wherein the upper semiconductor package further comprises a signal wire and a power wire,

wherein the upper package substrate comprises an upper chip signal wiring line, a lower chip signal wiring line, and a memory chip power wiring line,

wherein the signal wire is electrically connected to the upper semiconductor chip, and

wherein the upper chip signal wiring line electrically connects the signal wire to the signal connector.

20. The semiconductor package according to claim 16 , wherein the semiconductor chip comprises a lower semiconductor chip and an upper semiconductor chip on the lower semiconductor chip,

wherein the upper semiconductor package further comprises a signal wire and a power wire,

wherein the upper package substrate comprises an upper chip signal wiring line, a lower chip signal wiring line, and a memory chip power wiring line,

wherein the signal wire is electrically connected to the lower semiconductor chip, and

wherein the lower chip signal wiring line electrically connects the signal wire to the signal connector.

21. The semiconductor package according to claim 1 , wherein the exposed portion of the power connector is configured to contact a power bump for electrically connecting to an external board.