Efficient frequency detectors for clock and data recovery circuits
A system and method for a frequency detector circuit includes: a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input; a first circuit configured to generate a second edge output; a second circuit configured to generate a third edge output; and a combinational logic configured to output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high and configured to output a DOWN output when the first edge output, the second edge output, and the third edge output are all low.
1. A method of frequency detection comprising:
sampling a data input to obtain an odd data sample of the input data (Dodd);
sampling the data input to obtain an odd crossing sample of the input data (Xodd);
sampling the data input to obtain an even data sample of the input data (Deven);
sampling the data input to obtain an even crossing sample of the input data (Xeven);
generating an UP odd signal according to the Dodd, Xodd, and Deven samples;
generating a DOWN odd signal according to the Dodd, Xodd, and Deven samples;
generating an UP even signal according to the Deven, Xeven, and Dodd samples; and
generating a DOWN even signal according to the Deven, Xeven, and Dodd samples.
2. The method of frequency detection of claim 1 , wherein generating the UP odd signal according to the Dodd, Xodd, and Deven samples comprises:
determining an odd first edge signal according to the Dodd and Xodd samples, wherein the odd first edge signal is high when the Dodd and Xodd samples have different values;
determining an odd second edge signal according to the Xodd and Deven samples, wherein the odd second edge signal is high when the Xodd and Deven samples have different values; and
outputting the UP odd signal when the odd first edge signal and the odd second edge signal are both high.
3. The method of frequency detection of claim 1 , wherein generating the DOWN odd signal according to the Dodd, Xodd, and Deven samples comprises:
determining an odd first edge signal according to the Dodd and Xodd samples, wherein the odd first edge signal is high when the Dodd and Xodd samples have different values;
determining an odd second edge signal according to the Xodd and Deven samples, wherein the odd second edge signal is high when the Xodd and Deven samples have different values; and
outputting the DOWN odd signal when the odd first edge signal and the odd second edge signal are both low.
4. The method of frequency detection of claim 1 , wherein generating the UP even signal according to the Deven, Xeven, and Dodd samples comprises:
determining an even first edge signal according to the Deven and Xeven samples, wherein the even first edge signal is high when the Deven and Xeven samples have different values;
determining an even second edge signal according to the Xeven and Dodd samples, wherein the even second edge signal is high when the Xeven and Dodd samples have different values; and
outputting the UP even signal when the even first edge signal and the even second edge signal are both high.
5. The method of frequency detection of claim 1 , wherein generating the DOWN even signal according to the Deven, Xeven, and Dodd samples comprises:
determining an even first edge signal according to the Deven and Xeven samples, wherein the even first edge signal is high when the Deven and Xeven samples have different values;
determining an even second edge signal according to the Xeven and Dodd samples, wherein the even second edge signal is high when the Xeven and Dodd samples have different values; and
outputting the DOWN even signal when the even first edge signal and the even second edge signal are both LOW.
6. The method of frequency detection of claim 1 , further comprising temporally aligning the Dodd, Xodd, and Deven samples.
7. The method of frequency detection of claim 6 , further comprising temporally aligning the Deven, Xeven, and Dodd samples.
8. The method of frequency detection of claim 1 , further comprising providing a mode selection signal to engage a frequency detection mode.
9. The method of frequency detection of claim 1 , wherein the Dodd sample is sampled based on a first clock,
wherein the Xodd sample is sampled based on a second clock,
wherein the Deven sample is sampled based on a third clock,
wherein the Xeven sample is sampled based on a fourth clock, and
wherein the first clock, the second clock, the third clock, and the fourth clock are spaced 90 degrees apart.
10. A frequency detector circuit comprising:
a first slicer configured to sample a data input to output an odd data sample (Dodd);
a second slicer configured to sample the data input to output an odd crossing sample (Xodd);
a third slicer configured to sample the data input to output an even data sample (Deven);
a fourth slicer configured to sample the data input to output an even crossing sample (Xeven); and
a combinational logic circuit configured to:
generate an UP odd signal according to the Dodd, Xodd, and Deven samples;
generate a DOWN odd signal according to the Dodd, Xodd, and Deven samples;
generate an UP even signal according to the Deven, Xeven, and Dodd samples; and
generate a DOWN even signal according to the Deven, Xeven, and Dodd samples.
11. The frequency detector circuit of claim 10 , wherein the combinational logic circuit is further configured to generate the UP odd signal according to Deven, Xeven, and Dodd samples by:
determining an odd first edge signal according to the Dodd and Xodd samples, wherein the odd first edge signal is high when the Dodd and Xodd samples have different values;
determining an odd second edge signal according to the Xodd and Deven samples, wherein the odd second edge signal is high when the Xodd and Deven samples have different values; and
outputting the UP odd signal when the odd first edge signal and the odd second edge signal are both high.
12. The frequency detector circuit of claim 10 , wherein the combinational logic circuit is further configured to generate the DOWN odd signal according to the Dodd, Xodd, and Deven samples by:
determining an odd first edge signal according to the Dodd and Xodd samples, wherein the odd first edge signal is high when the Dodd and Xodd samples have different values;
determining an odd second edge signal according to the Xodd and Deven samples, wherein the odd second edge signal is high when the Xodd and Deven samples have different values; and
outputting the DOWN odd signal when the odd first edge signal and the odd second edge signal are both low.
13. The frequency detector circuit of claim 10 , wherein the combinational logic circuit is further configured to generate the UP even signal according to the Deven, Xeven, and Dodd samples by:
determining an even first edge signal according to the Deven and Xeven samples, wherein the even first edge signal is high when the Deven and Xeven samples have different values;
determining an even second edge signal according to the Xeven and Dodd samples, wherein the even second edge signal is high when the Xeven and Dodd samples have different values; and
outputting the UP even signal when the even first edge signal and the even second edge signal are both high.
14. The frequency detector circuit of claim 10 , wherein the combinational logic circuit is further configured to generate the DOWN even signal according to the Deven, Xeven, and Dodd samples by:
determining an even first edge signal according to the Deven and Xeven samples, wherein the even first edge signal is high when the Deven and Xeven samples have different values;
determining an even second edge signal according to the Xeven and Dodd samples, wherein the even second edge signal is high when the Xeven and Dodd samples have different values; and
outputting the DOWN even signal when the even first edge signal and the even second edge signal are both LOW.
15. The frequency detector circuit of claim 10 , further comprising:
a first data alignment circuit configured to temporally align the Dodd, Xodd, and Deven samples.
16. The frequency detector circuit of claim 15 , further comprising:
a second data alignment circuit configured to temporally align the Deven, Xeven, and Dodd samples.
17. The frequency detector circuit of claim 10 , further comprising a mode selection circuit configured to receive a mode selection signal to engage a frequency detection mode.
18. The frequency detector circuit of claim 10 , wherein the first slicer is configured to sample the data input according to a first clock,
wherein the second slicer is configured to sample the data input according to a second clock,
wherein the third slicer is configured to sample the data input according to a third clock,
wherein the fourth slicer is configured to sample the data input according to a fourth clock, and
wherein the first clock, the second clock, the third clock, and the fourth clock are spaced 90 degrees apart.