Devices and methods for layout-dependent voltage handling improvement in switch stacks
Devices and methods for layout-dependent voltage handling improvement in switch stacks. In some embodiments, a switching device can include a first terminal and a second terminal, a radio-frequency signal path implemented between the first terminal and the second terminal, and a plurality of switching elements connected in series to form a stack between the second terminal and ground. The stack can have an orientation relative to the radio-frequency signal path, and the switching elements can have a non-uniform distribution of a first parameter based in part on the orientation of the stack.
1. A method for fabricating a radio-frequency switching device, the method comprising:
providing a semiconductor substrate;
forming a plurality of field-effect transistors on the semiconductor substrate such that the field-effect transistors have a non-uniform distribution of a first parameter based at least in part on an orientation of the field-effect transistors relative to a radio-frequency signal path; and
connecting the field-effect transistors to form a stack, such that the non-uniform distribution results in the stack having a first voltage handling capacity that is greater than a second voltage handling capacity corresponding to a similar stack having a substantially uniform distribution of the first parameter.
2. The method of claim 1 wherein a first orientation of the stack corresponds to a first non-uniform distribution of the first parameter.
3. The method of claim 2 wherein the first orientation of the stack includes placement of the stack at 180° relative to the placement of the radio-frequency signal path.
4. The method of claim 2 wherein a second orientation of the stack corresponds to a second non-uniform distribution of the first parameter.
5. The method of claim 4 wherein the second orientation of the stack includes placement of the stack at 0° or 90° relative to the placement of the radio-frequency signal path.
6. The method of claim 1 wherein each of the plurality of field-effect transistors has a source, a drain, and a gate formed on an active region.
7. The method of claim 6 wherein each field-effect transistor is implemented as a finger configuration device such that the gate includes a number of rectangular shaped gate fingers, each gate finger implemented between a rectangular shaped source finger of the source contact and a rectangular shaped drain finger of the drain contact.
8. The method of claim 6 wherein the first parameter is of a set of one or more of a physical characteristic, an electrical characteristic, a chemical characteristic, and a mechanical characteristic of each field-effect transistor.
9. The method of claim 8 wherein the first parameter includes a length of the gate of each field-effect transistor.
10. The method of claim 9 wherein the non-uniform distribution of the gate length is further based in part on a non-uniform distribution of a second parameter associated with the field-effect transistors.
11. The method of claim 10 wherein the second parameter includes a distribution of voltage VDS across each field-effect transistor.
12. The method of claim 11 wherein the non-uniform distribution of the gate length is selected to yield a scaled version of the voltage VDS distribution.
13. The method of claim 12 wherein the scaled version of the voltage VDS distribution is based on scaling of the highest value of a voltage VDS distribution corresponding to a substantially uniform distribution of the gate length.
14. The method of claim 9 wherein a gate length of at least a first field-effect transistor of the stack having a first orientation is greater than a value of a uniform distribution of gate length of field-effect transistors of a corresponding stack, and a gate length of at least the first field-effect transistor of the stack having a second orientation is less than the value of the uniform distribution of the gate length.
15. The method of claim 14 wherein at least some of the field-effect transistors of the stack having the first orientation have gate lengths that are less than the value of the uniform distribution of the gate length and at least some of the field-effect transistors of the stack having the second orientation have gate lengths that are less than the value of the uniform distribution of the gate length.
16. The method of claim 15 wherein the sum of the VDS values of the field-effect transistors for the non-uniform distribution of the gate length is greater than the sum of the VDS values of the field-effect transistors for the uniform distribution of the gate length.
17. The method of claim 9 wherein the non-uniform distribution of the gate length includes a plurality of groups of gate length values, each group having a common value of the gate length.
18. The method of claim 1 wherein the non-uniform distribution of the first parameter is further based in part on the distance of the stack from the radio-frequency signal path.