IP Library Granted Patent US 11,227,794
Granted Patent B2
US 11,227,794 · App. 16/721,762 · Granted Jan 18, 2022

Method for making self-aligned barrier for metal vias In-Situ during a metal halide pre-clean and associated interconnect structure

Inventors: Sung-Li Wang (Hsinchu County, TW); Shuen-Shin Liang (Hsinchu County, TW); Yu-Yun Peng (Hsinchu, TW); Fang-Wei Lee (Hsinchu, TW); Chia-Hung Chu (Taipei, TW); Mrunal Abhijith Khaderbad (Hsinchu, TW); Keng-Chu Lin (Pingtung County, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H01L21/76816H01L21/02063H01L21/02068H01L21/28562H01L21/30604H01L21/7685H01L21/76849H01L21/76856H01L21/76864H01L21/76879H01L21/76883H01L21/76897H01L23/5226H01L23/53223H01L23/53252H01L23/53266
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Quick Facts
Patent No.
US 11,227,794
App. No.
16/721,762
Granted
Jan 18, 2022
Kind
B2
Abstract

A multi-layer interconnect structure with a self-aligning barrier structure and a method for fabricating the same is disclosed. For example, the method includes forming a via through an interlayer dielectric (ILD) layer, an etch stop layer (ESL), and a contact structure, pre-cleaning the via with a metal halide, forming a barrier structure on the contact structure in-situ during the pre-cleaning of the via with the metal halide, and depositing a second metal in the via on top of the barrier structure.

Claims (39)

1. A method, comprising:

forming a via through an interlayer dielectric (ILD) layer, an etch stop layer (ESL), and a contact structure;

pre-cleaning the via with a metal halide;

forming a barrier structure on the contact structure in-situ during the pre-cleaning of the via with the metal halide; and

depositing a second metal in the via on top of the barrier structure.

2. The method of claim 1 , wherein the ESL comprises a metal oxide.

3. The method of claim 2 , wherein the ESL comprises aluminum oxide.

4. The method of claim 1 , wherein a metal of the barrier structure is the metal used in the metal halide.

5. The method of claim 4 , wherein the metal comprises tungsten (W), Titanium (Ti), Tantalum (Ta), Aluminum (Al), Antimony (Sb), Arsenic (As), Bismuth (Bi), Cadmium (Cd), Cobalt (Co), Gallium (Ga), Germanium (Ge), Hafnium (Hf), Indium (In), Lead (Pb), Manganese (Mn), Silicon (Si), Tin (Sn), or Zinc (Zn).

6. The method of claim 1 , wherein the forming comprises:

heating a hydrogen halide formed from a reaction of the metal halide with the ESL to form a hydrogen gas and a halide gas; and

reacting the hydrogen gas with the metal halide to form the metal and the hydrogen halide.

7. The method of claim 1 , further comprising:

forming a metal nitride layer on the barrier structure before the second metal is deposited on top of the barrier structure.

8. A method, comprising:

forming a via through an interlayer dielectric (ILD) layer, an etch stop layer (ESL), and a contact structure;

pre-cleaning the via with a metal halide;

forming a barrier structure on the contact structure in-situ during the pre-cleaning of the via with the metal halide;

cleaning an interface of the barrier structure with a hydrogen plasma clean; and

depositing a second metal in the via on top of the barrier structure.

9. The method of claim 8 , wherein the via is recessed into the contact structure by less than 5 nanometers.

10. The method of claim 8 , wherein the barrier structure has a thickness above a top surface of the ESL that is less than 5 nanometers.

11. The method of claim 8 , wherein the ESL may consume less than 2 nanometers per side of the barrier structure during the hydrogen plasma clean.

12. The method of claim 8 , wherein an overall thickness of the barrier structure is a function of temperature, etching time, flow rate of the metal halide, and a thickness of the ESL.

13. The method of claim 8 , wherein a shape of the barrier structure is a function of a grain size of a metal of the metal halide, a grain structure of the metal of the metal halide, and an aspect ratio of the via.

14. The method of claim 8 , wherein a metal of the barrier structure is the metal used in the metal halide.

15. The method of claim 14 , wherein the metal comprises tungsten (W), Titanium (Ti), Tantalum (Ta), Aluminum (Al), Antimony (Sb), Arsenic (As), Bismuth (Bi), Cadmium (Cd), Cobalt (Co), Gallium (Ga), Germanium (Ge) Hafnium (Hf), Indium (In), Lead (Pb), Manganese (Mn), Silicon (Si), Tin (Sn), or Zinc (Zn).

16. The method of claim 8 , wherein the forming comprises:

heating a hydrogen halide formed from a reaction of the metal halide with the ESL to form a hydrogen gas and a halide gas; and

reacting the hydrogen gas with the metal halide to form the metal and the hydrogen halide.

17. A multi-layer interconnect structure, comprising:

a contact structure formed on a source-drain;

a metal oxide etch stop layer formed on the contact structure;

an interlayer dielectric (ILD) layer formed on the metal oxide etch stop layer;

a barrier structure formed in the contact structure, wherein the barrier structure is formed in-situ during a metal halide clean; and

a via formed through the ILD layer on the barrier structure, wherein the via is filled with a second metal.

18. The multi-layer interconnect structure of claim 17 , wherein a bottom surface of the barrier structure is curved.

19. The multi-layer interconnect structure of claim 17 , wherein a bottom surface of the barrier structure is flat.

20. The multi-layer interconnect of claim 17 , wherein a bottom surface of the barrier structure is formed via a plurality of angled segments.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 6, 2020
From: WANG, SUNG-LI; LIANG, SHUEN-SHIN; PENG, YU-YUN; LEE, FANG-WEI; CHU, CHIA-HUNG; KHADERBAD, MRUNAL ABHIJITH; LIN, KENG-CHU
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 051746/0141 →
Continuity (1)
Related Publication 20210193511A1 · Jun 24, 2021
Cited By (2)
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